FIELD OF THE INVENTION

The present invention relates to a superlattice avalanche photodiode, especially to a mesa structure superlattice avalanche photodiode with a planar p-n junction having high reliability for optical communication.

BACKGROUND OF THE INVENTION

For adapting to an optical communication system operating at high speed, high sensitivity and high reliability, semiconductor light receiving devices are required to be able to operate in a wave length of 1.3 to 1.6µm at high speed, high gain-bandwidth (GB) product, low dark current and high reliability. On pages 38 to 40, Volume 40(1), Appl. Phys. Lett. 1982, by F. Capasso et al., an invention by which ionization rate ratio α/β is increased by using conduction band-edge discontinuity ΔEc of superlattice for impact ionization of electrons has been proposed. On pages 1419 to 1423, J. Quantum Electronics, Volume 28(6), 1992, by Kagawa et al., an invention by which ionization rate ratio α/β is increased by using an InGaAsP/InAlAs system of superlattice with light sensitivity in a wavelength of 1.3 to 1.6µm for long distance optical communication has been proposed. The ionization rate ratio α/β is increased up to 5 in contrast to that up to 2 by Bulk InGaAs.

According to the superlattice structure, conduction band-edge discontinuity ΔEc is 0.39eV which is larger than 0.03eV of valence band-edge discontinuity ΔEv, so that electrons have more energy than holes by band-edge discontinuity when the electrons and holes get in a well layer. That means electrons reach the threshold energy of ionization, whereby the ionization rate ratio is increased and low noise operation can be realized.

With the above mentioned avalanche photodiode, however, leakage current is generated due to interface level between semiconductor layers (multiplication layer, field buffer layer and light absorption layer) on the side surface of a mesa structure and an SiN passivation layer, and a residual oxide layer and defect on the surface. The leakage current causes dark current to increase to 0.8µA up to several µA in a practical multiplication factor of 10 to 20, whereby more noise is generated. The passivation boundary surface is unstable at an atmosphere temperature of 200°C and reverse current 100µA, which are general condition for reliability test.

Nakamura et al. fabricated a superlattice APD (Avalanche Photo Diode) using a polyimide layer as a mesa passivation layer, on pages 261 to 264, TuC5-4, ECOC, 1991. In this structure, there are many interface level (more than 2 × 10¹²cm^-2eV), on the boundary surface between the polyimide layer and semiconductor layers (multiplication layer, field buffer layer and light absorption layer) on the side surface of the mesa structure. This kind of interface level generally is caused by dangling bond on the boundary surface between semiconductor and polyimide layer, between semiconductor native oxide layer and semiconductor, and on surface defect, etc. Generally, in the semiconductor layers depleted in reverse bias, the first dangling bond tends to be generated in a p^- InGaAs light absorption layer having a relatively smaller forbidden bandgap, and the last dangling bond tends to be generated in a superlattice multiplication layer including aluminum atomics which can be natural-oxidized easily. In high electric field (500 to 600kV/cm), µA order of surface-leakage dark current is generated based on those interface level. As time, the interface level and surface defect is increased due to hot-carrier injection effect into the passivation layer, and therefore, dark current is increased. To mesa type of photodiodes in which semiconductor depletion layer is exposed on the side surface, surface leakage current is large and becomes unstable as time.

With a planar type of device, described in a Japanese Patent Publication Kokai H4-10478, p^- type material having a carrier concentration of less than 10¹⁶cm^-3 is doped into a superlattice multiplication layer, however, it is difficult to realize this kind of doping into mixed crystal by general crystal growth method precisely.

SUMMARY OF THE INVENTION

Accordingly, an object of the invention is to provide an improved superlattice avalanche photodiode having low surface leakage dark-current.

This object is achieved by an superlattice avalanche photodiode according to claim 1 or claim 10. The dependent claims are related to different advantageous aspects and embodiments of the present invention.

According to a first aspect of the invention, a superlattice avalanche photodiode includes an electric field buffer layer, a superlattice multiplication layer and a cap layer, they been laminated. Around a mesa side surface, a round shape p⁺ region is formed to have a width of several µm by doping p⁺ to below the field buffer layer, and then the cap layer is etched so that the p⁺ region is not contact with the cap layer. This makes distance of several µm between the inner surface of the p⁺ region and the external surface of the cap layer. In this structure, even if a depletion layer, which is extending from the p-n junction to the light absorption layer, extends laterally toward the side surface of the mesa structure, the depletion layer does not reach the side surface of the mesa structure. That means no depletion layer reaches the passivation layer because a depletion layer of the light absorption layer is protected by a non-depletion region of semiconductor. A depletion layer extending from the p-n junction toward the superlattice multiplication layer extends to the boundary surface between the passivation layer and the n⁺ cap layer (and etching stopper layer if it is used), however, electric field intensity in the lateral direction is less than 300kV/cm because the p⁺ region and the n⁺ cap layer are not in contact with each other. That is, because only semiconductor having low electric field and a large forbidden band width is in contact with the passivation layer, mealy low surface leakage current flows. According to the structure of the invention, electric field intensity on a region, to which electric field is applied, exposed on the interface of the passivation layer is remarkably reduced.

Practically, the superlattice avalanche photodiode according to the first aspect of the invention includes a first conductive type of semiconductor substrate; a first conductive type of semiconductor buffer layer provided on the semiconductor substrate; a first conductive type of semiconductor light absorption layer provided on the semiconductor buffer layer; a first conductive type of semiconductor electric-field buffer layer formed on the semiconductor light absorption layer; a superlattice multiplication layer provided on the semiconductor electric-field buffer layer; a second conductive type of semiconductor cap layer provided on the superlattice multiplication layer; a second conductive type of semiconductor contact layer provided on the semiconductor cap layer; and a first conductive type of selective region selectively formed, around a photo-sensitive region, inwardly from the surface of the contact layer so as to reach at least under the electric-field buffer layer; wherein the selective region is formed so as to be separated from either the semiconductor cap layer and contact layer by etching.

According to a second aspect of the invention, a peripheral region around a cap layer has a smaller amount of an electric-field drop relative to the region just below the cap layer, so that field little edge multiplication can be realized. For reducing field drop, impurity implantation or diffusion is used. The impurity can be Fe, Ti, Co, H, O, etc. which forms high resistance layer by itself. If the first conducive type of field buffer layer has a thickness which is thinner at the peripheral to have a smaller amount of field drop, the superlattice multiplication layer has lower electric intensity at the peripheral relative to the center in response to the same bias voltage (area).

Practically, a superlattice avalanche photodiode according to the second aspect of the invention includes a first conductive type of semiconductor substrate; a first conductive type of semiconductor buffer layer provided on the semiconductor substrate; a first conductive type of semiconductor light absorption layer provided on the semiconductor buffer layer; a first conductive type of semiconductor electric-field buffer layer formed on the semiconductor light absorption layer; a superlattice multiplication layer provided on the semiconductor electric-field buffer layer; a second conductive type of semiconductor cap layer provided on the superlattice multiplication layer; a second conductive type of semiconductor contact layer provided on the semiconductor cap layer; and a first conductive type of selective region selectively formed, around a photo-sensitive region, inwardly from the surface of the contact layer so as to reach at least under the electric-field buffer layer; wherein the selective region is formed so as to have higher resistance selectively at a region being contact with the semiconductor cap layer and contact layer.

BRIEF DESCRIPTION OF THE DRAWINGS

• Fig. 1 is a cross-sectional view showing a first conventional semiconductor light receiving device.
• Fig. 2 is a cross-sectional view showing a second conventional semiconductor light receiving device.
• Fig. 3 is a cross-sectional view showing a third conventional semiconductor light receiving device.
• Fig. 4 is a cross-sectional view showing a semiconductor light receiving device of a first preferred embodiment according to the invention.
• Fig. 5 is a cross-sectional view showing a semiconductor light receiving device of a second preferred embodiment according to the invention.
• Fig. 6 is a cross-sectional view showing a semiconductor light receiving device of a third preferred embodiment according to the invention.
• Figs. 7 and 8 are graphs showing the operation of the first to third preferred embodiments.
• Fig. 9 is a cross-sectional view showing a semiconductor light receiving device of a fourth preferred embodiment according to the invention.
• Fig. 10 is a cross-sectional view showing a semiconductor light receiving device of a fifth preferred embodiment according to the invention.
• Fig. 11 is a graph showing the operation of the fourth and fifth preferred embodiments.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

For better understanding of the invention, a conventional technology is first described. Fig. 1 shows a first conventional superlattice avalanche photodiode, which includes an n⁺ type of InP substrate 31, an n⁺ type of InP buffer layer 32 provided on the InP substrate 31, an n^- type of InGaAsP/InAlAs superlattice multiplication layer 33 provided on the buffer layer 32, a p type of InP electric-field buffer layer 34 provided on the superlattice multiplication layer 33, a p^-

type of InGaAs light absorption layer 35 provided on the field buffer layer 34, a p⁺ type of InP cap layer 36 provided on the light absorption layer 35, a p⁺ type of InGaAs contact layer 37 provided on the cap layer 36, an n-electrode 38 provided on the reverse surface of the substrate 31, a p-electrode 39 connected to the contact layer 37, an SiN passivation layer 310 provided almost over the entire structure and a polyimide layer 311 provided on the side surface of the SiN passivation layer 310.

According to the above mentioned avalanche photodiode, as described before, however, leakage current is generated due to interface level between semiconductor layers (superlattice multiplication layer 33, field buffer layer 34 and light absorption layer 35) on the side surface of the mesa structure and the SiN passivation layer 310, and a residual oxide layer and defect on the surface. The leakage current causes dark current to increase to 0.8 up to several µA in a practical multiplication factor of 10 to 20, whereby more noise is generated. The passivation boundary surface is unstable at an atmosphere temperature of 200°C and reverse current 100µA, which are general condition for reliability test.

Fig. 2 shows a second conventional superlattice avalanche photodiode, which includes an n⁺ type of InP substrate 41, an n⁺ type of InAlAs buffer layer 42 provided on the InP substrate 41, an n^- type of InGaAs/InAlAs superlattice multiplication layer 43 provided on the buffer layer 42, a p type of InAlAs electric-field buffer layer 44 provided on the superlattice multiplication layer 43, a p^- type of InGaAs light absorption layer 45 provided on the field buffer layer 44, a p⁺ type of InAlAs cap layer 46 provided on the light absorption layer 45, a p⁺ type of InGaAs contact layer 47 provided on the cap layer 46, an n-electrode 48 provided on the reverse surface of the substrate 41, a p-electrode 49 connected to the contact layer 47, a polyimide passivation layer 410 provided almost over the entire structure and a reflection preventing layer 411 provided on the contact layer 47.

According to the above mentioned avalanche photodiode, as described before, however, there are many interface level (more than 2 × 10¹²cm^-2eV), on the boundary surface between the polyimide layer and semiconductor layers (superlattice multiplication layer 43, field buffer layer 44 and light absorption layer 45) on the side surface of the mesa structure. In high electric field (500 to 600kV/cm), pm order of surface-leakage dark current is generated based on those interface level. As time, the interface level and surface defect is increased due to hot-carrier injection effect into the passivation layer, and therefore, dark current is increased. To mesa type of photodiodes in which semiconductor depletion layer is exposed on the side surface, surface leakage current is large and becomes unstable as time.

Fig. 3 shows a third conventional planar type of device, which includes a p⁺ type of InP substrate 51, a p⁺ type of InP buffer layer 52 provided on the InP substrate 51, a p^- type of InGaAs light absorption layer provided on the buffer layer 52, a p type of InGaAs electric-field buffer layer 54 provided on the light absorption layer 53, a p type of InGaAs/InAlAs superlattice multiplication layer 55 provided on the field buffer layer 54, a p type of InP cap layer 56 provided on the superlattice multiplication layer 55, a high concentration n type of InP region 57 formed in the cap layer 56, a low concentration n type of InP region 58 formed in the cap layer 56, an AuGeNi ohmic electrode 59 provided on the reverse surface of the substrate 51 to have a light input window thereon, and an AuZnNi ohmic electrode 510 provided on the cap layer 56.

According to the above mentioned device, as described before, however, it is difficult to perform doping into mixed crystal by general crystal growth method precisely.

Fig. 4 shows a superlattice avalanche photodiode of a first preferred embodiment according to the invention, which includes a p⁺ type of InP substrate 11, a p⁺ type of InP buffer layer 12 provided on the InP substrate 11 to have a thickness of 0.5 to 1.0µm, a p^- type of InGaAs light absorption layer 13 provided on the buffer layer 12 to have a carrier concentration of up to 2×10¹⁵cm^-3 and a thickness of 1.0 to 1.5µm, a p⁺ type of InP electric-field buffer layer 14 provided on the light absorption layer 13 to have a carrier concentration of 0.5 to 1×10¹⁸cm^-3 and a thickness of 0.1 to 0.05µm (depending on the carrier concentration of the field buffer layer 14), a non-doped i-type or n-type InAlGaAs/InAlAs superlattice multiplication layer 15 provided on the field buffer layer 14 having a carrier concentration of up to 2×10¹⁵cm^-3 to have a thickness of 0.23µm, an InP etching stopper layer 115 provided on the superlattice multiplication layer 15 to have a thickness of 0.005 to 0.05µm, an n⁺ type of InAlAs cap layer 16 provided on the stopper layer 115 to have a carrier concentration of up to 1×10¹⁸cm^-3 to have a thickness of 0.5µm, an n⁺ type of InGaAs contact layer 17 provided on the cap layer 16 to have a carrier concentration of up to 1×10¹⁹cm^-3 to have a thickness of 0.1µm, an n-electrode 18 of AuGeNi connected to the contact layer 17, a p-electrode 19 of AuZn connected to the buffer layer 12, a p⁺ type of conductive region 110 provided on the stopper layer 115, an anti-reflection cating film 111 of SiN provided on the reverse surface of the semiconductor substrate 11, and a passivation layer 112.

In fabrication, the layers 12, 13, 14, 15 115, 16 and 17 are grown in the order by gas source MBE (Molecular Beam Epitaxy) method. The InP etching stopper layer 115 may be omitted. The p⁺ type of conductive region 110 is formed by Zn selective thermal diffusion using a round shape SiN layer having a diameter of 30µm as a mask to have a carrier concentration of 1×10¹⁸cm^-3 to 1×10¹⁹cm^-3. The p⁺ type of conductive region 110 is diffused in depth below the InP field buffer layer 14. The InP cap layer 16 and InGaAs contact layer 17 are etched at the boundary with the p⁺ type conductive region 110 to the etching stopper layer 115 so as to remove the boundary region to be ring shape having a width of several µm. The entire structure is etched to the buffer layer 12 to have a mesa shape. The reverse surface of the substrate 11 is polished and the anti-reflection coating film 111 is formed thereon.

Fig. 5 shows a superlattice avalanche photodiode of a second preferred embodiment according to the invention, which includes a p⁺ type of InP substrate 11, a p⁺ type of InP buffer layer 12 provided on the InP substrate 11 to have a thickness of 0.5 to 1.0µm, a p^- type of InGaAs light absorption layer 13 provided on the buffer layer 12 to have a carrier concentration of up to 2×10¹⁵cm^-3 and a thickness of 1.0 to 1.5µm, a p⁺ type of InP electric-field buffer layer 14 provided on the light absorption layer 13 to have a carrier concentration of 0.5 to 1×10¹⁸cm^-3 and a thickness of 0.1 to 0.05µm (depending on the carrier concentration of the field buffer layer 14), a non-doped i-type or n-type InAlGaAs/InAlAs superlattice multiplication layer 15 provided on the field buffer layer 14 having a carrier concentration of up to 2×10¹⁵cm^-3 to have a thickness of 0.23µm, an InP etching stopper layer 115 provided on the superlattice multiplication layer 15 to have a thickness of 0.005 to 0.05µm, an n⁺ type of InAlAs (or InP) cap layer 16 provided on the stopper layer 115 to have a carrier concentration of up to 1×10¹⁸cm^-3 to have a thickness of 0.5µm, an n⁺ type of InGaAs contact layer 17 provided on the cap layer 16 to have a carrier concentration of up to 1×10¹⁹cm^-3 to have a thickness of 0.1µm, an n-electrode 18 of AuGeNi connected to the contact layer 17, a p-electrode 19 of AuZn connected to the buffer layer 12, a p⁺ type of conductive region 110 provided on the stopper layer 115, an anti-reflection coating film 111 of SiN provided on the reverse surface of the semiconductor substrate 11, and a passivation layer 112.

In fabrication, the layers 12, 13, 14, 15 115, 16 and 17 are grown in the order by gas source MBE (Molecular Beam Epitaxy) method. The InP etching stopper layer 115 may be omitted. The p⁺ type of conductive region 110 is formed by Zn selective thermal diffusion using a round shape SiN layer having a diameter of 30µm as a mask to have a carrier concentration of 1×10¹⁸cm^-3 to 1×10¹⁹cm^-3. The p⁺ type of conductive region 110 is diffused in depth below the InP field buffer layer 14, usually to the buffer layer 12. In the ring shape boundary portion, a high resistance region 113 is formed by ion implantation of O⁺, H⁺, Ar⁺ Fe⁺, Ti or Co to reach the superlattice multiplication layer 15. After the ion implantation, the entire structure may be annealed to activate it. After that, the entire structure is etched to the buffer layer 12 to have a mesa shape. The reverse surface of the substrate 11 is polished and the reflection preventing layer 111 is formed thereon.

Fig. 6 shows a superlattice avalanche photodiode of a third preferred embodiment according to the invention, which includes a p⁺ type of InP substrate 11, a p⁺ type of InP buffer layer 12 provided on the InP substrate 11 to have a thickness of 0.5 to 1.0µm, a p^- type of InGaAs light absorption layer 13 provided on the buffer layer 12 to have a carrier concentration of up to 2×10¹⁵cm^-3 and a thickness of 1.0 to 1.5µm, a p⁺ type of InP electric-field buffer layer 14 provided on the light absorption layer 13 to have a carrier concentration of 0.5 to 1×10¹⁸cm^-3 and a thickness of 0.1 to 0.05µm (depending on the carrier concentration of the field buffer layer 14), a non-doped i-type or n-type InAlGaAs/InAlAs superlattice multiplication layer 15 provided on the field buffer layer 14 having a carrier concentration of up to 2×10¹⁵cm^-3 to have a thickness of 0.23µm, an InP etching stopper layer 115 provided on the superlattice multiplication layer 15 to have a thickness of 0.005 to 0.05µm, an n⁺ type of InAlAs cap layer 16 provided on the stopper layer 115 to have a carrier concentration of up to 1×10¹⁸cm^-3 to have a thickness of 0.5µm, an n⁺ type of InGaAs contact layer 17 provided on the cap layer 16 to have a carrier concentration of up to 1×10¹⁹cm^-3 to have a thickness of 0.1µm, an n-electrode 18 of AuGeNi connected to the contact layer 17, a p-electrode 19 of AuZn connected to the buffer layer 12, a p⁺ type of conductive region 110 provided on the stopper layer 115, an anti-reflection coating film 111 of SiN provided on the reverse surface of the semiconductor substrate 11, and a passivation layer 112.

In fabrication, the layers 12, 13, 14, 15 115, 16 and 17 are grow in the order by gas source MBE (Molecular Beam Epitaxy) method. The InP etching stopper layer 115 may be omitted. The p⁺ type of conductive region 110 is formed by Zn selective thermal diffusion using a round shape SiN layer having a diameter of 30µm as a mask to have a carrier concentration of 1×10¹⁸cm^-3 to 1×10¹⁹cm^-3. The p⁺ type of conductive region 110 is diffused in depth below the InP field buffer layer 14, usually to the buffer layer 12. The InP cap layer 16 and InGaAs contact layer 17 are etched at the boundary with the p⁺ type conductive region 110 to the etching stopper layer 115 using an SiN or SiO₂ layer as a mask so as to remove the boundary region to be ring shape having a width of several µm. After that, an InP semiconductor buried layer 114 is selectively re-grown in the etched region using the same mask. Before the re-growth, it is preferable to do thermal cleaning or removing of surface oxide layer by using hydrogen radical beam. The entire structure is etched to the buffer layer 12 to have a mesa shape. The reverse surface of the substrate 11 is polished and the reflection preventing layer 111 is formed thereon.

As shown in Figs. 7 and 8, according to the first to third preferred embodiments, only a region of the superlattice multiplication layer 15 just below the n⁺ cap layer 16 has a high electric field of around 600kV/cm, so that the boundary surface with the passivation layer does not have a higher electric field. Although a region being in contact with the passivation layer to which electric field is applied is the etching stopper layer 115 (or superlattice multiplication layer) at a space between the cap layer 16 and the region 110, electric field intensity is less than 300kV/cm because of the space of several µm. Further, by the first to third preferred embodiments, 120GHz of GB product can be obtained for high speed response, and initial dark current which is the same as that by conventional technology is detected. After a test of reliability, for example at 200°C of atmosphere temperature, with 100µA of reverse current for 100 hours, the initial dark current has not been increased and the device has not been damaged.

Fig. 9 shows a superlattice avalanche photodiode of a fourth preferred embodiment according to the invention, which includes a p⁺ type of InP substrate 11, a p⁺ type of InP buffer layer 12 provided on the InP substrate 11 to have a thickness of 0.5 to 1.0µm, a p^- type of InGaAs light absorption layer 13 provided on the buffer layer 12 to have a carrier concentration of up to 2×10¹⁵cm^-3 and a thickness of 1.0 to 1.5µm, a p⁺ type of InP electric-field buffer layer 14 provided on the light absorption layer 13 to have a carrier concentration of 0.5 to 1×10¹⁸cm^-3 and a thickness of 0.1 to 0.05µm (depending on the carrier concentration of the field buffer layer 14), a non-doped i-type or n-type InAlGaAs/InAlAs superlattice multiplication layer 15 provided on the field buffer layer 14 having a carrier concentration of up to 2×10¹⁵cm^-3 to have a thickness of 0.23µm, an InP etching stopper layer 115 provided on the superlattice multiplication layer 15 to have a thickness of 0.005 to 0.05µm, an n⁺ type of InAlAs cap layer 16 provided on the stopper layer 115 to have a carrier concentration of up to 1×10¹⁸cm^-3 to have a thickness of 0.5µm, an n⁺ type of InGaAs contact layer 17 provided on the cap layer 16 to have a carrier concentration of up to 1×10¹⁹cm^-3 to have a thickness of 0.1µm, an n-electrode 18 of AuGeNi connected to the contact layer 17, a p-electrode 19 of AuZn connected to the buffer layer 12, a p⁺ type of conductive region 110 provided on the stopper layer 115, an anti-reflection coating film 111 of SiN provided on the reverse surface of the semiconductor substrate 11, and a passivation layer 112.

In fabrication, the layers 12, 13, 14, 15 115, 16 and 17 are grown in the order by gas source MBE (Molecular Beam Epitaxy) method. The InP etching stopper layer 115 may be omitted. Ion implantation and activation is selectively carried out to be a ring shape 117 with each of Fe, Ti, Co, H and O or a combination thereof using a round shape mask having an inner diameter of 20µm and outer diameter of more than 30µm. The ion implantation is carried out to at least deeper than the field buffer layer 14 so as to reduce the concentration of a region 116 in the buffer layer 14. Next, the region 110 is formed by Zn selective thermal diffusion using a round shape SiN mask having a diameter of 30µm to have a carrier concentration of about 1×10¹⁹cm^-3. The region 110 is diffused in depth below the InP field buffer layer 14. The InP cap layer 16 and InGaAs contact layer 17 are etched at the boundary with the p⁺ type conductive region 110 to reach the surface of the superlattice multiplication layer 15 so as to remove the boundary region to be ring shape having a width of several µm. After that, the entire structure is etched to the buffer layer 12 to have a mesa shape. The reverse surface of the substrate 11 is polished and the reflection preventing layer 111 is formed thereon.

Fig. 10 shows a superlattice avalanche photodiode of a fifth preferred embodiment according to the invention, which includes a p⁺ type of InP substrate 11, a p⁺ type of InP buffer layer 12 provided on the InP substrate 11 to have a thickness of 0.5 to 1.0µm, a p^- type of InGaAs light absorption layer 13 provided on the buffer layer 12 to have a carrier concentration of up to 2×10¹⁵cm^-3 and a thickness of 1.0 to 1.5µm, a p⁺ type of InP electric-field buffer layer 14 provided on the light absorption layer 13 to have a carrier concentration of 0.5 to 1×10¹⁸cm^-3 and a thickness of 0.1 to 0.05µm (depending on the carrier concentration of the field buffer layer 14), a non-doped i-type or n-type InAlGaAs/InAlAs superlattice multiplication layer 15 provided on the field buffer layer 14 having a carrier concentration of up to 2×10¹⁵cm^-3 to have a thickness of 0.23µm, an InP etching stopper layer 115 provided on the superlattice multiplication layer 15 to have a thickness of 0.005 to 0.05µm, an n⁺ type of InAlAs cap layer 16 provided on the stopper layer 115 to have a carrier concentration of up to 1×10¹⁸cm^-3 to have a thickness of 0.5µm, an n⁺ type of InGaAs contact layer 17 provided on the cap layer 16 to have a carrier concentration of up to 1×10¹⁹cm^-3 to have a thickness of 0.1µm, an n-electrode 18 of AuGeNi connected to the contact layer 17, a p-electrode 19 of AuZn connected to the buffer layer 12, a p⁺ type of conductive region 110 provided on the stopper layer 115, an anti-reflection coating film 111 of SiN provided on the reverse surface of the semiconductor substrate 11, and a passivation layer 112.

In fabrication, the layers 12 to 14 are crystal-grown on the substrate 11, then, an outer region 118 of the InP field buffer layer 14 other than an round shaped inner region having a diameter of 20µm is etched by 0.005 to 0.05µm depending on the carrier concentration of the field buffer layer 14 itself. After that, the layers 15 to 17 are grown in the order by gas source MBE (Molecular Beam Epitaxy) method, MOVPE method, etc. The p⁺ type conductive region is formed by Zn selective thermal diffusion using a round shape SiN mask having a diameter of 30µm to have a carrier concentration of about 1×10¹⁹cm^-3. The region is diffused in depth below the InP field buffer layer 14, usually to the buffer layer 12. The InP cap layer 16 and InGaAs contact layer 17 are etched at the boundary with the p⁺ type conductive region 110 to reach the surface of the superlattice multiplication layer 15 so as to remove the boundary region to be ring shape having a width of several µm. After that, the entire structure is etched to the buffer layer 12 to have a mesa shape. The reverse surface of the substrate 11 is polished and the reflection preventing layer 111 is formed thereon.

In these embodiments, a semi-insulation InP substrate can be used instead of the p type of semiconductor substrate 11. The substrate may have height difference on its surface to use characteristics of impurity concentration change and/or a thickness change on the patterned substrate in semiconductor crystal growth.

As shown in Fig. 11, according to the fourth and fifth preferred embodiments, the peripheral region around the cap layer has a smaller amount of electric-field drop relative to the portion just below the cap layer 16 so that electric field intensity around the superlattice multiplication layer 15 is low whereby little edge multiplication can be realized. For reducing field drop, impurity implantation or diffusion is used. The impurity can be Fe, Ti, Co, H, O, etc. which forms high resistance layer by itself. If the first conducive type of field buffer layer has a thickness which is thinner at the peripheral to have a smaller amount of field drop, the superlattice multiplication layer has lower electric field intensity at the peripheral relative to the center in response to the same bias voltage. These two embodiments have an advantage in uniformity of increase characteristics especially in a bias of more than ten multiplication factor.