Duty cycle control system专利检索-施密特触发器电子零件及设备专利检索查询-专利查询网

Duty cycle control system

阅读：856发布：2022-01-21

专利汇可以提供Duty cycle control system专利检索，专利查询，专利分析的服务。并且A closed loop control system for controlling the average output of a generator or other device. The output is detected and the detected signal is applied to a summing point at which it is summed with an externally supplied control signal. The summed signal is integrated and applied to a Schmidt Trigger, the output of which is coupled through control logic to control the generator. The generator duty cycle is controlled to maintain a desired average output. In a specific embodiment wherein the average output of a three phase converter supplying D.C. to the generator is controlled, at each duty cycle the converter is turned on at an initial reference potential crossing point and thereafter the output is a function of the difference between the most positive and the least positive phases.，下面是Duty cycle control system专利的具体信息内容。

权利要求

1. 1An on-off duty cycle control circuit for an electrical device powered by a d.c. voltage supply derived from a threephase a.c. voltage source through three-element controlled rectifier devices each of which has an anode connected to one of said three-phase voltages, said circuit comprising: a. means generating a two level signal indicative of the on-off state of the electrical device to be controlled, b. means generating a second signal of a magnitude indicative of the desired on-off duty cycle of said electrical device, c. means receiving said two level signal and said second signal and generating therefrom a summed signal, d. means receiving said summed signal and generating an integrated summed signal, e. means receiving said integrated summed signal and generating in dependence of the magnitude and slope of said integrated summed signal a control signal of a first magnitude for an ''''on'''' period and of a second magnitude for the ''''off'''' period of said desired duty cycle, f. means receiving said control signal and voltages from each of the three phases of said a.c. source and generating during said ''''on'''' period three series of trigger pulses, each of said series for application to the control electrode of a different one of said controlled rectifier devices, each of said trigger pulses being timed to occur when the phase voltage of the anode of the controlled rectifier to which said trigger pulse is to be applied becomes the most positive of the three phase voltages of said a.c. source.

2. A control circuit as defined in claim 1 wherein said last named means further includes means generating an initial trigger pulse during each of said ''''on'''' periods for application to the control electrode of the one of said controlled rectifiers whose anode was at the reference voltage of said a.c. source at the beginning of said ''''on'''' period, said initial trigger pulse being timed to occur as said anode becomes more positive than said reference voltage.

3. In an on-off duty cycle control circuit for an electrical device powered by a d.c. power supply derived from a a.c. source having phase voltage A, B and C through three-element controlled rectifier devices, each of which has an anode connected to one of said phase voltages, a logic circuit for triggering said controlled rectifier devices comprising: a. first, second and third comparator means, said first comparator means having phases A and C as inputs, said second comparator means having phases A and B as inputs and said third comparator means having phases B and C as inputs, the output of each of said comparator means being a square wave signal having leading edges and trailing edges; b. first, second and third logic means having an enable input and coupled to be responsive to leading edges of, respectively, the first, second and third square wave signals; c. fourth, fifth and sixth logic means having an enable input and coupled to be responsive to trailing edges of, respectively, the first, second and third square wave signals; d. seventh logic means coupled to the output of said first logic means and to the output of said fifth logic means, the output of said seventh logic means being coupled to trigger the controlled rectifier device of phase A; e. eighth logic means coupled to the output of said second logic means and to the output of said sixth logic means, the output of said eighth logic means coupled to trigger the controlled rectifier device of phase B; and f. ninth logic means coupled to the output of said third logic means and to the output of said fourth logic means, the output of said ninth logic means coupled to trigger the controlled rectifier device of phase C.

4. The circuit of claim 3 further comprising means for enabling said fourth, fifth and sixth logic means and disabling said first, second and third logic means in response to a run signal.

5. The circuit of claim 4 further comprisiNg means for enabling said first, second and third logic means and disabling said fourth, fifth and sixth logic means in response to the first-occurring trailing edge.

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