专利汇可以提供Highly conductive source/drain contacts in III-nitride transistors专利检索,专利查询,专利分析的服务。并且In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors. In another embodiment, a structure for highly conductive source/drain contacts is disclosed.,下面是Highly conductive source/drain contacts in III-nitride transistors专利的具体信息内容。
The invention claimed is:
In the present application, “III-Nitride,” “III-Nitride device,” “III-Nitride transistor,” III-Nitride semiconductor,” and the like refer to compound semiconductors that include nitrogen and at least one group III element, such as, but not limited to, GaN, AlGaN, InN, AlN, InGaN, InAlGaN and the like.
1. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of fabrication of semiconductor transistors.
2. Background Art
Prior to the present invention, metallic diffusion barriers have been used in gate, source, and drain regions. Materials used for such diffusion barriers include titanium nitride. Such diffusion barriers, while providing useful functions, such as electrical conduction to the layers below, and providing a barrier against diffusion of subsequent undesirable materials into underlying regions when forming various regions, such as gate regions in a field effect transistor (FET) and/or in a high electron mobility transistor (HEMT) in III-Nitride technology, have presented certain disadvantages. For example, in adding such diffusion barriers, the resistance between the source/drain contacts and the source/drain regions in a FET or HEMT is increased. Such increased resistance diminishes the performance of transistors, such as current carrying capability and speed of transistors, which are specially important in III-Nitride power transistors, such as III-Nitride HEMTs.
It would be advantageous to reduce resistance between drain and source contacts and the respective underlying drain and source regions, while still using diffusion barriers, such as titanium nitride for the remaining portions of the transistors, such as part of the gates in FETs and/or HEMTs.
The present invention is directed to highly conductive source/drain contacts in III-Nitride transistors, substantially as shown in and/or described in connection with at least one of the figures, and as set forth in the claims.
The present invention is directed to highly conductive source/drain contacts in III-Nitride transistors. Although the invention is described with respect to specific embodiments, the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the invention described herein. Moreover, in the description of the present invention, certain details have been left out in order to not obscure the inventive aspects of the invention. The details left out are within the knowledge of a person of ordinary skill in the art.
The drawings in the present application and their accompanying detailed description are directed to merely example embodiments of the invention. To maintain brevity, other embodiments of the invention, which use the principles of the present invention, are not specifically described in the present application and are not specifically illustrated by the present drawings. It should be borne in mind that, unless noted otherwise, like or corresponding elements among the Figures may be indicated by like or corresponding reference numerals.
It is to be noted that the drawings in the present application, such as
Beginning with step 110 in
Field dielectric layer 240 may include known field dielectric materials such as silicon nitride, which may or may not be stoichiometric silicon nitride. Also, in one or more embodiments, such deposition of field dielectric layer 240 may be formed by a low-pressure chemical vapor deposition (LPCVD) or another process. Field dielectric layer 240 generally results in a reduction of electric field between overlying interconnect lines and underlying III-Nitride semiconductor body 242. In one embodiment, field dielectric layer 240 may also serve to passivate the underlying AlGaN layer. In another embodiment, such passivation may also arise from optional thin GaN layer 252 either alone or in conjunction with field dielectric layer 240.
Referring to
Continuing on to step 112 in
Continuing with step 114 of flowchart 100 and structure 214 in
As indicated in step 116 of flowchart 100 and structure 216 of
Continuing with step 120 of flowchart 100 and structure 220 in
Continuing to
As shown in structure 224 of
As shown by structure 226 of
This, intermediate structure 228 as shown in
Continuing on to step 130 of the flowchart 100 in
In one embodiment, gate dielectric portions remain after step 130 and include a source/drain trench sidewall gate dielectrics 286 and gate dielectric horizontal protrusions 288. In a preferred embodiment, step 130 includes retaining sidewall gate dielectrics 286 and gate dielectric horizontal protrusions 288 of gate dielectric 270 to cover corners 284 of dielectric trenches 260 and 264. The retained trench sidewall gate dielectrics 286 and gate dielectric horizontal protrusions 288 result in improved or “stuffed-corner” source and drain contacts, which provide protection from subsequent damage to regions defining the source and drain dimensions and result in more predictable source and drain geometries and functions.
Thus, as shown in
In an alternative embodiment, step 130 may result in removal of gate dielectric horizontal protrusions 288, or both gate dielectric horizontal protrusions 288 and trench sidewall gate dielectrics 286. These embodiments are not explicitly shown in the drawings.
Once gate dielectric layer 270 has been removed from the bottoms of dielectric trenches 260 and 264 according to step 130 and structure 230, contact metal 290 may be deposited in dielectric trenches 260 and 264 to form ohmic metal contacts with the top surfaces of source and drain regions 254 and 258 according to step 132 of flowchart 100 in
Upon completion of the steps shown in flowchart 100 of
From the above description of the invention, it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. The described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.
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