专利汇可以提供FINFET BASED ZRAM WITH CONVEX CHANNEL REGION专利检索,专利查询,专利分析的服务。并且Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.,下面是FINFET BASED ZRAM WITH CONVEX CHANNEL REGION专利的具体信息内容。
What is claimed is:
The present invention relates generally to semiconductor fabrication, and more particularly, to fabrication of ZRAM devices.
Dynamic random access memory (DRAM) is utilized in many electronic devices. These include computers, mobile devices, tablets, and consumer electronics, to name a few. A continuous goal is increasing of the circuit density, thus increasing the amount of memory in a physical package. This enables increasingly powerful computing power in smaller, more portable devices. Zero capacitance random access memory (ZRAM) is a type of DRAM memory based on the floating body effect. In ZRAM, the floating body effect allows the memory cell to be built without adding a separate capacitor, as the floating body effect takes the place of the conventional capacitor. However, there are various fabrication challenges to making ZRAM devices in a reliable, and cost effective manner. It is therefore desirable to have improved structures and methods for implementation of ZRAM devices.
In a first aspect, embodiments of the present invention provide a semiconductor structure, comprising: a semiconductor substrate; a semiconductor fin disposed on the semiconductor substrate; a channel region comprising: a finned channel portion; and a convex channel portion disposed around the finned channel portion, wherein the channel region comprises an elongated surface and a short surface; a metal gate disposed around the elongated surface of the channel region; a first spacer disposed adjacent to the metal gate and in direct physical contact with the short surface of the channel region; and a second spacer disposed adjacent to the first spacer.
In a second aspect, embodiments of the present invention provide a semiconductor structure, comprising: a semiconductor substrate; a semiconductor fin disposed on the semiconductor substrate; a channel region comprising: a finned channel portion; and a convex channel portion disposed around the finned channel portion, wherein the channel region comprises an elongated surface and a short surface; a metal gate disposed around the elongated surface of the channel region and the short surface of the channel region; and a spacer disposed adjacent to the metal gate.
In a third aspect, embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a semiconductor fin on a semiconductor substrate; forming a sacrificial gate structure; forming a first spacer adjacent to the sacrificial gate structure; forming a second spacer adjacent to the first spacer; forming source/drain regions adjacent to the second spacer; removing the sacrificial gate structure; forming a convex channel region; and forming a metal gate structure.
The structure, operation, and advantages of the present invention will become further apparent upon consideration of the following description taken in conjunction with the accompanying figures (FIGs.). The figures are intended to be illustrative, not limiting.
Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity.
Often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG). Furthermore, for clarity, some reference numbers may be omitted in certain drawings.
Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices. Such devices, sometimes referred to as ZRAM devices, implement a dynamic random access memory without the use of a capacitor in each storage cell. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer. This arrangement can provide a structure that is compatible with replacement metal gate processes to enable increased flexibility in design and manufacture of ZRAM devices.
The channel region 231 is a so-called convex channel because it is wider than the fin. In embodiments, the convex channel portion 234 is comprised of silicon germanium (SiGe), and the finned channel portion 236 is comprised of silicon (which does not include germanium). In embodiments, the germanium concentration of the SiGe that comprises the convex channel portion 234 ranges from about 20 percent to about 40 percent, by atomic weight. In other embodiments, the convex channel portion 234 comprises indium phosphide (InP), and the finned channel portion 236 is comprised of silicon or silicon germanium. In other embodiments, the convex channel portion 234 comprises silicon (which does not include germanium), and the finned channel portion 236 comprises indium. In some embodiments, the finned channel portion 236 may include, but is not limited to, indium phosphide (InP), indium arsenide (InAs), and/or indium gallium arsenide (InGaAs). In other embodiments, the convex channel portion 234 comprises silicon and also includes germanium (SiGe).
A first spacer 228 is disposed adjacent to the gate 224 and in direct physical contact with the short surface 239 of the channel region 231. Thus, the gate 224 is disposed only along the elongated side of the channel region 231, and the gate does not cover the short surface 239 of the channel region 231. In embodiments, the first spacer 228 may include, but is not limited to, hafnium oxide, titanium oxide, and/or zirconium oxide. The first spacer 228 is preferably a High-K (K>4) material. A second spacer is disposed adjacent to the first spacer. In embodiments, the second spacer is comprised of silicon oxide. Disposed adjacent to the second spacer 226 is source/drain regions 220. The source/drain regions 220 may comprise an epitaxially grown semiconductor material such as epitaxial silicon or epitaxial silicon germanium. Doped extension regions 238 may extend into the channel region 231.
As can now be appreciated, embodiments of the present invention provide improved methods and structures for fabricating finFET-based ZRAM devices comprising convex channels, which are compatible with replacement metal gate processes. Embodiments may use either an N-type finFET or a P-type finFET. Some embodiments may comprise one fin per memory cell. Other embodiments may use multiple fins per memory cell. For example, in one embodiment, three fins per memory cell are used. Using multiple fins per memory cell can serve to reduce device variability.
Although the invention has been shown and described with respect to a certain preferred embodiment or embodiments, certain equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.) the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more features of the other embodiments as may be desired and advantageous for any given or particular application.
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