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High burnout resistance schottky barrier diode

阅读:634发布:2023-11-01

专利汇可以提供High burnout resistance schottky barrier diode专利检索,专利查询,专利分析的服务。并且A semiconductor rectifier device particularly suited for mixing and/or detecting electric wave signals in the microwave frequency range and having a high resistance to RF burnout is disclosed. A semiconductive region having an impurity concentration greater than a prescribed amount is located in a semiconductor body of opposite polarity to the region. A metal in face to face contact with the region and the semiconductor body forms an N-type and a P-type Schottky-barrier junction. A PN junction is also defined at the interface of the semiconductive region and semiconductor body such that under the influence of a low signal level no injection occurs at the PN junction but under the influence of a high signal level large injection occurs at the PN junction causing a large change in the impedance and capacitance of the device. As a result the semiconductor device, previously matched to the line at low RF signal level becomes mismatched and highly reflective of RF energy at high RF signal level, thus preventing burnout. (For the purposes of this disclosure low signal level is defined as 1-2 mW. typically of electromagnetic energy but no greater than 50 mW. per diode, whereas high signal level is any electromagnetic energy over 50 mW.,下面是High burnout resistance schottky barrier diode专利的具体信息内容。

1. A semiconductor rectifier device particularly suited for mixing and detecting electric wave signals in the microwave frequency range and having high resistance to RF burnout comprising: a. A body of elemental semiconductor; b. Said body including therein a semiconductive region having an impurity concentration greater than 1 X 1018/cm.3 and of polarity opposite to that of said body; c. A PN junction defined by the boundary of said semiconductive region and said semiconductor body such that under the influence of electromagnetic wave energy at a level not greater than about 50 mW substantially no carrier injection occurs at said junction, but under the influence of such energy at a level greater than about 50 mW substantial carrier injection occurs at said junction, causing a substantial change in the capacitance of and hence the impedance exhibited to said energy by said junction; d. A metal in electrical contact with said semiconductor body and with said semiconductive region, said metal being disposed in face to face contact with said semiconductor body and said semiconductive region, said semiconductive region being offset in relation to the center area of said face to face contact and not necessarily surrounding said face to face contact, said metal forming a first metal semiconductor junction with said body of semiconductor and a second metal semiconductor junction with said semiconductive region, said first metal semiconductor junction having a polarity opposite to that of second metal semiconductor junction.
2. A semiconductor device as recited in claim 1 in which said body of semiconductor has an epitaxial layer of semiconductor on it, and said semiconductive region has an impurity concentration greater than 1 X 1018/cm.3, said PN junction, said first and second metal-semiconductor junctions existing exclusively in said epitaxial layer.
3. A semiconductor device as recited in claim 1 wherein said semiconductor body is selected from the group consisting of silicon, germanium, and gallium arsenide.
4. A semiconductor device as recited in claim 1 wherein said metal in contact with said semiconductive region and said semiconductor body is selected from the group consisting of nickel, molybdenum, tungsten, gold, silver, copper, aluminum, platinum and palladium.
5. A semiconductor device as recited in claim 1 wherein said semiconductor body is P-type silicon.
6. A semiconductor device as recited in claim 1 wherein said semiconductor body is an N-type silicon.
7. A semiconductor device as recited in claim 1 including means for protecting said PN junction, first and second junctions, against environmental contamination.
8. A semiconductor device as recited in claim 7 wherein said protective means comprises a silicon oxide mask on a portion of the surface of said semiconductor body.
9. A semiconductor device as recited in claim 1 including packaging means having at least two integral electrodes for electrical connection to circuitry within said packaging means, said electrodes being electrically separated one from the other by dielectric means and extending to the exterior of said packaging means for electrical connection to external circuitry, said semiconductor body being bonded to one of said electrodes, and said metal being bonded to the other of said electrodes.
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