Signal generators employing digital phase locked loops and compensating circuits
阅读：790发布：2021-07-13
专利汇可以提供Signal generators employing digital phase locked loops and compensating circuits专利检索，专利查询，专利分析的服务。并且There is described a signal generator capable of being tuned over a relatively high frequency range. The generator includes a VCO which is controlled in frequency by a phase locked loop. The loop operates to compare a reference frequency from an accurate crystal source with the divided oscillator frequency. The division is afforded by a first frequency counter which controls a programmable divider to cause the same to divide by the correct integer independent of the oscillator tuning. The phase locked loop includes a phase detector responsive to digital waveforms to provide a dual polarity error control signal by combining outputs of the phase detector in a differential operational amplifier. The operational amplifier is further controlled to cancel an error offset voltage so that the final output signal is free from spurious modulation products.，下面是Signal generators employing digital phase locked loops and compensating circuits专利的具体信息内容。
1. A signal generator of the type employing a voltage controlled oscillator, whose frequency is compared and stabilized by means of a phase locked loop including a programmable divider network for developing another frequency indicative of said oscillator frequency and comparing it with an accurate reference frequency, in combination therewith phase detecting apparatus for providing an error voltage when said other frequency is not in synchronism with said reference frequency, comprising: a. first means responsive to said another frequency for converting the same to a first pulse series having the repetition rate of said another frequency and a narrow pulse width, b. second means responsive to said accurate reference frequency for converting the same to a second pulse series having the repetition rate of said reference frequency and said narrow pulse width, c. first and second bistable circuits each having at least two trigger inputs and an output, said bistable circuits capable of being in any one of two stable states under control of a suitable signal applied to any one of said trigger inputs, one of said inputs of said first bistable coupled to said first means, and said corresponding input of said second bistable coupled to said second means, said other input of said first bistable coupled to said second means while said corresponding input of said second bistable coupled to said first means, to cause said first bistable to provide a first error signal at its output when saId another frequency is lower than said reference, and to cause said second bistable to provide a second error signal when said another frequency is higher than said reference frequency, d. an operational amplifier of the type which undesireably provides an offset error signal, said operational amplifier having a first non-inverting input and a second inverting input and arranged as an integrator, said operational amplifier biased to provide a first polarity DC signal for said first error signal applied to said non-inverting input and a second opposite polarity DC signal for said second error signal applied to said inverting input, said offset error signal undesireably appearing at the output of said operational amplifier even when said another frequency and said reference signal are equal, e. means coupled to the output of said operational amplifier and responsive to said offset error signal for providing another DC signal indicative of the magnitude and polarity of said offset error signal, and f. control means coupled to said operational amplifier and responsive to said another DC signal for varying the characteristic of said amplifier in a direction to cancel said offset signal.
2. The signal generator according to claim 1 wherein said control means coupled to said operational amplifier comprises: a. a source of light responsive to said another DC signal for providing a variable intensity light signal according to the magnitude of said DC signal, and b. a photo-resistor optically coupled to said source of light and coupled to said operational amplifier to alter the operating characteristics thereof according to said intensity to thereby eliminate said offset error signal.
3. A phase locked loop of the type including a phase detector for developing an error voltage when the frequency of an oscillator to be controlled deviates from the frequency of a reference signal, said phase detector error signal being applied to an operational amplifier arranged in an integrating configuration for developing a DC voltage used to control the frequency of said oscillator in a direction such that it is made to substantially equal said frequency of said reference signal, said operational amplifier of the type that undesirably provides an offset error signal when said oscillator and said reference signal are substantially equal, said offset error signal characterized by having a repetition rate according to said reference frequency, in combination therewith apparatus for eliminating said offset error signal comprising, a. a synchronous detector responsive to said reference signal and said offset error signal to provide at an output a DC control signal indicative of the magnitude and phase of said offset signal, b. means coupling said output of said synchronous detector to said operational amplifier to cause said amplifier to respond to said DC control signal in a direction to eliminate said offset error signal.
4. The apparatus according to claim 3 wherein said means coupling said output of said synchronous detector to said operational amplifier comprises, a. a source of light coupled to said output of said synchronous detector and driven thereby to emit a variable intensity of light according to the magnitude of said offset error signal, and b. a photo resistor optically coupled to said source of light and coupled to said operational amplifier to alter the operating characteristics thereof according to said intensity to thereby eliminate said offset error signal.
5. A signal generator of the type employing a voltage controlled oscillator, whose frequency is compared and stabilized by means of a phase locked loop including a programmable divider network for developing another frequency indicative of said oscillator frequency and comparing it with an accurate reference frequency, in combination therewith phase detecting apparatus for providing an error voltage when said other frequency is not in synchronism wiTh said reference frequency, comprising: a. first and second bistable multivibrators, each having at least a first and a second input terminal, each of said terminals responsive to a trigger signal to change the state of said bistable multivibrator at said output terminal, b. means coupling said programmable divider to said first input terminal of said first multivibrator and to said second input terminal of said second multivibrator, c. means for applying said reference frequency to said second input terminal of said first multivibrator and to said first input terminal of said second multivibrator, to cause one of said multivibrators to change state when said another frequency is higher than said reference and said other to change state when said reference frequency is higher than said another frequency, d. amplifying means having a first inverting and a second non-inverting input terminal and an output terminal, said first input terminal coupled to said first multivibrator, said second input terminal coupled to said second multivibrator, to provide at an output of said amplifying means said error voltage capable of controlling said oscillator so that said other frequency is in synchronism with said reference frequency, said amplifying means further operative to provide a spurious error signal unrelated to any frequency difference between said other frequency and said reference frequency, said spurious error signal undesireably operative to offset the frequency of said oscillator, e. means coupled to said output terminal of said amplifying means and responsive to said reference frequency to provide at an output a control signal determinative of the magnitude and phase of said spurious error signal, and f. means coupled to said amplifying means and responsive to said control signal to vary the characteristics of said amplifying means in a direction to cancel said spurious error signal.
6. Apparatus using a phase detector for providing at outputs a first and second DC error signal by comparing the phase of a reference signal with a signal from a source to be controlled, said phase detector employing an operational amplifier having an inverting and non-inverting input for combining first and second error signals from said detector, to provide a single dual polarity signal therefrom, said operational amplifier undesirably having an input offset error which causes a given AC error signal to appear at the output thereof when the frequencies of said signal from said controlled source and said reference signal are substantially equal, in combination therewith apparatus for eliminating said given AC error signal comprising, a. detecting means operative in response to said reference signal and responsive to said AC error signal for providing at an output a DC signal determinative of the magnitude and phase of said AC error signal, b. means coupling said output of said detector to said operational amplifier to cause said amplifier to vary its characteristics according to said DC signal in a direction to cancel said AC error signal.
7. In combination: a. a variable oscillator capable of being tuned over a relatively large band of frequencies, said oscillator having a frequency control input adapted to receive a DC control voltage for varying the frequency thereof according to the polarity and magnitude of said DC control voltage, b. a first frequency counter coupled to said oscillator and operative to store a count therein representative of the frequency of said oscillator, c. a second programmable counter having a plurality of inputs for presetting said programmable counter to cause said counter to divide an input signal applied to an input terminal thereof by a predetermined integer, such that the output signal of said counter is relatively at a predetermined desired frequency, d. means coupling said first counter to said plurality of inputs of said programmable counter to preset said counter accordIng to said stored count, e. means coupling said programmable divider to said variable oscillator to cause said counter to divide said oscillator frequency according to said preset stored count to cause said programmable counter to provide said predetermined desired frequency independent of the setting of said oscillator, f. a reference signal source for providing a reference frequency substantially at said predetermined desired frequency, g. phase detecting means for comparing said reference signal with said output signal of said programmable divider to provide at an output an error signal indicative of any frequency difference therebetween, h. means responsive to said error signal, said means including a high gain operational amplifier which amplifier undesireably provides a spurious error signal, which signal has a DC component unrelated to any difference between said output signal of said programmable divider and said reference signal, said means having an output coupled to said frequency control input of said oscillator to cause said oscillator to provide a frequency dependent upon both said error signal and said spurious signal, i. detector means coupled to said high gain amplifier and responsive to said spurious error signal and said reference signal to provide a compensating signal at an output thereof indicative of the magnitude and phase of said spurious error signal, and j. means for applying said compensating signal to said means responsive to said error signal to substantially cancel the same to cause said oscillator to provide a frequency which when applied to said divider causes the same to provide said output signal at a frequency substantially equal to said frequency of said reference signal.
8. The combination according to claim 7 further comprising, a. switching means capable of being operated in a first and second state, said switching means being coupled to said first counter and to said variable oscillator, to permit said counter to accummulate said count representative of said oscillator frequency in said first state, while preventing said oscillator from varying its frequency until said count is accummulated and for preventing said first counter from accummulating said count in said second state.
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