PRIORITY CLAIM

The present application is a continuation of U.S. application Ser. No. 13/452,138, filed Apr. 20, 2012, which is incorporated herein by reference in its entirety.

BACKGROUND

A phase locked loop (PLL) is used to synchronize signals. PLLs are used in radio transceivers, telecommunications, clock multipliers, microprocessors and other devices which use synchronized signals. PLLs are used to synchronize the signals of two separate devices. As technology advances, a wider range of frequencies is used to synchronize separate devices. Also, as chip switching speed increases, a faster locking time for synchronizing signals of the two separate devices is desired. However, prior PLL designs exhibit a slow locking time, increased power consumption or increased chip size.

Prior techniques for using a PLL to lock two signals together in synchronization include wide-range digital logic quadricorrelator (WDLQ) based systems. WDLQ based systems have a long processing time, resulting in a slow locking time in comparison with other techniques. A counter based system exhibits a faster locking time than the WDLQ based system, but requires the inclusion of a high frequency clock and a counter which increases power consumption and chip size.

DESCRIPTION OF THE DRAWINGS

One or more embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout. It is emphasized that, in accordance with standard practice in the industry various features may not be drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features in the drawings may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a functional block diagram of a phase locked loop (PLL) including auto frequency calibration, according to one or more embodiments;

FIG. 2 is a block diagram of a code generator of a PLL, according to one or more embodiments;

FIG. 3 is a flow chart for a determination of a period number used by a code generator, according to one or more embodiments;

FIG. 4 is a flow chart for a determination of a coarse tuning signal output by a code generator, according to one or more embodiments; and

FIG. 5 is a flow chart of a method for using a PLL, according to one or more embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are examples and are not intended to be limiting.

FIG. 1 is a functional block diagram of a phase locked loop (PLL) 100. In some embodiments, PLL 100 is an all digital PLL (ADPLL). PLL circuit 100 includes a phase difference detector 102 configured to receive a reference frequency Fref and a divider frequency Fdiv. Phase difference detector 102 outputs a phase difference signal 103. A code generator 104 is configured to receive the phase difference signal 103, the reference frequency Fref and a sampling period number 105 (see FIG. 2). Code generator 104 outputs a coarse tuning signal 107a and a reset signal 107b. A digital loop filter 106 is configured to also receive the phase difference signal 103. Digital loop filter 106 outputs a fine tuning signal 109. A voltage controlled oscillator (VCO) 108 is configured to receive the coarse tuning signal 107a and the fine tuning signal 109. VCO 108 outputs an output frequency signal 111 to external circuitry. A divider 110 is configured to also receive a feedback of the output frequency signal 111. Divider 110 is also configured to receive the reset signal 107b as well as divider number control signal (N<4:0> and F<0:19>). Divider 110 outputs the divider frequency Fdiv which is received by phase difference detector 102. A delta-sigma modulator 112 is configured to receive a divisor ratio signal N.F and the reset signal 107b, where N is an integer portion of the divisor ratio signal and F is a fractional portion of the divisor ratio signal.

Phase difference detector 102 is configured to receive the reference frequency Fref and the divider frequency Fdiv and output the phase difference signal 103. In some embodiments, phase difference detector 102 comprises a time-to-digital converter (TDC). The TDC converts pulses into a digital representation of the time indices of the pulses. The TDC does not account for a magnitude of the pulses. In some embodiments, phase difference detector 102 comprising a time-to-current converter (TCC) and an analog-to-digital converter (ADC). The TCC converts pulses into an analog current signal of the time indices of the pulses. The ADC converts the analog current signal to a digital signal. The combination of the TCC and ADC is capable of accounting for a magnitude of the pulses of the reference frequency Fref, to help reduce erroneous pulse detection resulting from signal noise. In some embodiments, phase difference detector 102 compares a rising edge of the reference frequency Fref with a rising edge of the divider frequency Fdiv. In instances where the rising edge of the reference frequency Fref occurs before the rising edge of the divider frequency Fdiv, the reference frequency is said to be leading the divider frequency. The phase difference signal 103 is a positive value when the reference frequency Fref is leading the divider frequency Fdiv. In instances where the rising edge of the divider frequency Fdiv occurs before the rising edge of the reference frequency Fref, the divider frequency is said to be leading the reference frequency. The phase difference signal 103 is a negative value when the divider frequency Fdiv is leading the reference frequency Fref.

FIG. 2 is a block diagram of a code generator 200 (e.g. code generator 104). Code generator 200 includes a first comparator 202 configured to compare the phase difference signal 103 to a base-line signal 203. In some embodiments, the base-line signal 203 is equal to a zero logic level signal.

A counter 206 is configured to receive the reference frequency Fref and output a counter signal 207. A second comparator 208 is configured to receive the counter signal 207 and the sampling period number 105. Second comparator 208 outputs a control signal 209. The control signal 209 is a high logic value if the sampling period signal number 105 is equal to the counter signal 207. The control 209 is a low logic value if the sampling period number 105 is not equal to the counter signal 207. A multiplexer 210 is configured to receive the comparison signal 205, the coarse tuning signal 107a and the control signal 209. The control signal 209 acts as a selector for multiplexer 210. A register 212 is configured to receive the reference frequency Fref and an output of multiplexer 210. Register 212 outputs the coarse tuning signal 107a. A look-up table 214 is configured to provide the sampling period number 105 based on the fractional portion of the divisor ratio signal received from delta-sigma modulator 112.

First comparator 202 is configured to compare the phase difference signal 103 to the base-line signal 203. The output from first comparator 202 is a high logic level if the phase difference signal 103 is greater than the base-line signal 203, i.e., a positive value. The output from first comparator 202 is a low logic level if the phase difference signal 103 is not greater than the base-line signal 203, i.e., a negative value.

Counter 206 is configured to receive the reference frequency Fref and output the counter signal 207. Counter 206 is configured to count cycle numbers of the reference frequency Fref. In some embodiments, counter 206 counts the cycle numbers using a rising edge of the reference frequency Fref. In some embodiments, counter 206 comprises a flip-flop. Counter 206 is also configured to receive the reset signal 107b. When counter 206 receives the reset signal 107b, the cycle number in counter 206 is reset to zero.

Second comparator 208 is configured to receive the counter signal 207 and the sampling period number 105. Second comparator 208 is configured to determine whether a sampling period number 105 is equal to the counter signal 207. In some embodiments, a value of the sampling period number is determined on by five most significant bits (MSBs) of the fractional portion of the divisor ratio signal received from delta-sigma modulator 112. The control signal 209 is a high logic value if the counter signal 207 and the sampling period are equal. The control signal 209 is a low logic value if the counter signal 207 and the sampling period number are not equal.

FIG. 3 is a flow chart of a decision tree 300 for determining the value of the sampling number 105 based on the divider number control signal F<0:4>, which is the fractional portion of the divisor ratio signal received from delta-sigma modulator 112. Look-up table 214 is configured to receive the fractional portion of the divisor ratio. Based on a number of most significant bits (MSBs) of the fractional portion of the divisor ratio, look-up table 214 determines the value of the sampling period. In some embodiments, the number of MSBs is five. In some embodiments, the number of MSBs is greater than or less than five. The value of the sampling period is determined by t which has a value other than zero, starting with the least significant bit of the number of MSBs. For example, where F[0]-F[4] are the five MSBs of the, F[4] is examined first in determining the value of the sampling period.

In operation 302, look-up table 214 determines if F[M−1]=1, where M is the number of MSBs. In operation 304, if F[M−1]=1, then the sampling period N is set to 2^M+1. In operation 306, if F[M−1]=0, then look-up table 214 determines if the next bit, F[M−2], has a value. In operation 308, if F[M−2]=1, then the sampling period N is set to 2^(M-1)+1. In operation 310, if F[M−2]=0, the look-up table 214 examines the next bit. The process continues until bit F[0] is examined. In operation 312, look-up table 214 determines if F[0]=1. In operation 314, if F[0]=1, then the sampling period N is set to five. In operation 316, if F[0]=0, then the sampling period N is set to three.

Returning to FIG. 2, multiplexer 210 is configured to receive the comparison signal 205, the coarse tuning signal 107a and the control signal 209. The control signal 209 acts as the selector for multiplexer 210. Multiplexer 210 outputs the comparison signal 205 if the control signal 209 has a high logic value. Multiplexer 210 outputs the coarse tuning signal 107a if the control signal 209 has a low logic value. Multiplexer 210 uses the control signal 209 to control timing of changes to the coarse tuning signal 107a. In some embodiments, the coarse tuning signal 107a changes only if the counter signal 207 is equal to the sampling period.

Register 212 is configured to receive the reference frequency Fref and the coarse tuning signal 107a. Register 212 outputs the coarse tuning signal 107a based on the rising edge of the reference frequency Fref. In some embodiments, register 212 comprises a flip-flop. The coarse tuning signal 107a is used to either increase or decrease the frequency of the output frequency signal 111 from VCO 108.

FIG. 4 is a flow chart 400 for determining a value of the coarse tuning signal 107a output by a code generator (e.g. code generator 104). In operation 402, look-up table 214 determines sampling period N based on the fractional portion of the divisor ratio received from delta-sigma modulator 112. In some embodiments, look-up table 214 determines sampling period N based on the decision tree 300 of FIG. 3. In operation 404, code generator 104 determines if reference frequency Fref leads the divider frequency Fdiv at the sampling period N. In operation 406a, if reference frequency Fref leads divider frequency Fdiv at the sampling period N, code generator 104 outputs coarse tuning signal 107a equal to zero to increase the output frequency from VCO 108. In operation 406b, if reference frequency Fref does not lead divider frequency Fdiv at the sampling period N, code generator 104 outputs coarse tuning signal 107a having a high logical value which decreases the output frequency from VCO 108.

Following each output of the coarse tuning signal 107a, code generator 104 outputs the reset signal 107b to prepare PLL 100 for subsequent iterations of signal locking. In some embodiments, code generator 104 includes a reset signal generator. The reset signal generator is configured to receive the control signal 209. When the control signal 209 has a high logical value, the reset signal generator outputs the reset signal 107b.

Returning to FIG. 1, digital loop filter 106 is configured to receive the phase difference signal 103 and output the fine tuning signal 109. In some embodiments, digital loop filter 106 comprises a low pass filter. In some embodiments, digital loop filter 106 comprises a high pass filter. In some embodiments, digital loop filter 106 comprises a gain amplifier. Digital loop filter 106 is configured to have a smaller lock range than code generator 104. Lock range is the frequency range over which the PLL can lock the output frequency to the reference frequency Fref. By reducing the lock range of digital loop filter 106, locking time and stability of PLL 100 are increased. In some embodiments, digital loop filter 106 is deactivated while code generator 104 is in use. In some embodiments, digital loop filter 106 is activated after code generator 104 reduces a difference between the output frequency and the reference frequency Fref to a value within the lock range of digital loop filter 106. Once the output frequency is synchronized with the reference frequency Fref, digital loop filter 106 is used to compensate for subsequent fluctuations within the reference frequency Fref or the output frequency.

VCO 108 is configured to receive the coarse tuning signal 107a and the fine tuning signal 109 and output the output frequency signal 111 based on the coarse tuning signal 107a and the fine tuning signal 109. In some embodiments, VCO 108 is a relaxation oscillator. In some embodiments, VCO 108 is a digitally controlled oscillator (DCO). In some embodiments, VCO 108 comprises a capacitor. In some embodiments, VCO 108 comprises a trigger circuit such as a latch, a Schmitt trigger, a negative resistance element or other suitable circuit. VCO 108 is capable of changing a frequency of the output frequency signal 111 based on the coarse tuning signal 107a and the fine tuning signal 109. In some embodiments, a step size of the change in the frequency of the output frequency signal 111 based on the coarse tuning signal 107a is greater than a step size of the change in the frequency of the output frequency signal 111 based on the fine tuning signal 109.

Divider 110 is configured to receive the output frequency signal 111, the reset signal 107b and the divider number control signal. In some embodiments, divider 110 comprises a counter. Divider 110 is configured to divide the output frequency based on the divider number control signal F<0:4> and output the divider frequency Fdiv which is received by phase difference detector 102. Dividing the frequency output reduces the number of comparisons performed by PLL 100 in contrast to PLLs without a divider. The reduced number of comparisons facilitates smaller tuning steps, in contrast to PLLs without a divider, which in turn allow for more precise synchronization between the reference frequency Fref and the output frequency. The reset signal 107b from code generator 104 returns values stored in divider 110 to default values, e.g., sets a counting circuit to zero.

Delta-sigma modulator 112 is configured to receive the divisor ratio signal, N.F, where N is an integer component of the divisor ratio signal and F is a fractional component of the divisor ratio signal. Delta-sigma modulator 112 controls divider 110 by specifying a number of comparisons to be performed by PLL 100. Delta-sigma modulator 112 also provides the fraction component to code generator 104 to determine the sampling period. In some embodiments, delta-sigma modulator 112 is configured to dither the divider number to improve the phase noise performance of PLL 100. The reset signal 107b from code generator 104 causes the reset of values stored in delta-sigma modulator 112 to default values. In some embodiments, divisor ratio, N.F is selected by a user. In some embodiments, divisor ratio, N.F, is calculated based on a design of phase difference detector 102.

FIG. 5 is a flow chart of at least a portion of a method 500 for using a PLL (e.g. PLL 100). In operation 502, a phase difference between two signals is detected using a phase difference detector. The phase difference at the sampling period N is determined by phase difference detector 102 and transmitted to code generator 104 via the phase difference signal 103. The phase difference signal 103 is positive, if the reference frequency Fref leads the divider frequency Fdiv. The phase difference signal 103 is negative, if the divider frequency Fdiv leads the reference frequency Fref. Code generator 104 compares the phase difference signal 103 to zero at first comparator 202. The comparison result is transmitted to multiplexer 210.

In operation 504, an initial value of a fine tuning signal is set and a coarse tuning signal is generated based on the detected phase difference using a code generator. The initial value of the fine tuning signal is set using a divisor ratio. In some embodiments, the value of the divisor ratio is selected by a user. In some embodiments, the user inputs the divisor ratio using a man-machine interface such as a keyboard, a mouse or other suitable interface. In some embodiments, the value of the divisor ratio is calculated, using external circuitry, by dividing the reference frequency Fref by a comparator frequency. The comparator frequency is a rate at which phase difference detector 102 determines an offset between the reference frequency Fref and the divider frequency Fdiv.

The coarse tuning signal is generated based on the sampling period. The sampling period is determined based on a fractional value of the divisor ratio. In some embodiments, the sampling period is based on the five MSBs of the divisor ratio. In some embodiments, the sampling period is based on a different number of MSBs of the divisor ratio. In some embodiments, the sampling period is determined by delta-sigma modulator 112. In some embodiments, the sampling period is determined by code generator 104. In some embodiments, the sampling period is determined by second comparator 208. In some embodiments, the sampling period is determined using look up table 214 connected to second comparator 208.

Multiplexer 210 is configured to receive the comparison result and the control signal 209 from second comparator 208. An output of multiplexer 210 is received by register 212 which generates the coarse tuning signal.

In operation 506, an output frequency is changed according to a value of the coarse tuning signal. A determination is made by multiplexer 210 whether to increase or decrease the frequency of a voltage controlled oscillator. If the phase difference at the sampling period is positive, register 212 outputs a low logic value for the coarse tuning signal 107a and the frequency of VCO 108 increases. If the phase difference at the sampling period is negative, register 212 outputs a high logic value for the coarse tuning signal 107a and the frequency of VCO 108 decreases. Following output of the coarse tuning signal 107a, code generator 104 outputs the reset signal 107b to reset divider 110, delta-sigma modulator 112 and counter 206 to default values.

In operation 508, a fine tuning signal is generated based on the detected phase difference through a digital loop filter after all the bits of coarse tuning signal are decided. Fine tuning is performed using digital loop filter 106. Digital loop filter 106 has a smaller lock range than code generator 104. In some embodiments, digital loop filter 106 has a smaller step size than code generator 104. During fine tuning, digital loop filter 106 is used to compensate for fluctuations in the reference frequency Fref and other variances within PLL 100 to facilitate locking between the reference frequency Fref and the output reference.

In operation 510, the output frequency is fine tuned until the two signals are synchronized.

An aspect of this description relates to an apparatus that comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.

Another aspect of this description relates to a method that comprises generating a fine tuning signal using a digital loop filter based on a phase difference signal. The method also comprises generating a coarse tuning signal based on the phase difference signal and a reference frequency using a code generator. The method further comprises generating a reset signal using the code generator. The method additionally comprises generating an output signal using a voltage control oscillator based on the coarse tuning signal and the fine tuning signal. The method also comprises generating a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.

A further aspect of this description relates to a method that comprises generating a coarse tuning signal based on a phase difference signal using a code generator. The phase difference signal is based on a determined phase difference between a first signal and a second signal. The method also comprises generating a fine tuning signal based on the phase difference signal using a digital loop filter. The fine tuning signal has an initial value based on a rate at which the phase difference is determined by a phase difference detector. The method further comprises generating an output signal using a voltage control oscillator based on the coarse tuning signal and the fine tuning signal. The second signal is based on the output signal, and the output signal is tuned using the digital loop filter until the first signal and the second signal are synchronized.

It will be readily seen by one of ordinary skill in the art that the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.