专利汇可以提供Semiconductor device and manufacture thereof专利检索,专利查询,专利分析的服务。并且PURPOSE: To enable easy positioning and alignment of connection parts and also highly accurate and small-sized packaging by a method wherein flat wiring terminals of a chip having larger dimensions and bumps of a chip having smaller dimensions are made to oppose to each other.
CONSTITUTION: A first chip 1 is a chip, which is provided on the side of a substrate, and has comparatively large dimensions, a row of bumps 3 is provided along the peripheral edge part of the chip 1 and a row of pads 5 is provided along the inside of the row of bumps. A second chip is chip, which is provided on the side (over the first chip) opposite to the chip 1 in the case of assembly, and is formed as a chip having dimensions smaller by the width of the bump region of the chip 1 compared to the chip 1. A row of bumps 4 is provided at positions, where pads (wiring terminals) are normally provided, along the peripheral edge of the second chip. A carrier chip 16 consists of a flexible insulator, penetrated holes 17 are bores at prescribed intervals in the tape 16 and a plurality of Cu leads 6 are annexed encircling each hole 17. The side of the inner (inside) lead of each lead is provided facing each hole 17. The tape is positioned on the chip 1 and the bumps of the chip 1 and the leads are connected to one another.
COPYRIGHT: (C)1990,JPO&Japio,下面是Semiconductor device and manufacture thereof专利的具体信息内容。
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