Silicon gate complementary mos dynamic ram
阅读：362发布：2023-05-20
专利汇可以提供Silicon gate complementary mos dynamic ram专利检索，专利查询，专利分析的服务。并且A monolithic integrated circuit random access memory system having a storage matrix of silicon gate MOS N-channel dynamic RAM cells interfaced with silicon gate complementary MOS addressing circuitry, requiring no diffused guard rings, and input-output circuitry. Dynamic N-channel RAM cells are used to provide very high density storage of binary data in the relatively large storage matrix, and complementary silicon gate low threshold MOS circuitry is used to implement the peripheral circuitry including the address decoding sections, refresh circuitry, and inputoutput section to provide extremely low power dissipation, high speed operation, low sensitivity to device parameter variations, high noise immunity, and efficient operation over a wide range of power supply voltages.，下面是Silicon gate complementary mos dynamic ram专利的具体信息内容。
1. A monolithic random access memory array capable of accepting digital data in the form of electronic impulses from an outside data source, having a plurality of dynamic silicon gate MOS storage cells arranged in 2M rows and 2N columns, each cell being provided with selective input means, responsive to a relatively low or relatively high voltage level, arbitrarily indicative, respectively, of a binary 1 a binary 0 and each cell being provided with output means for indicating its binary data content, each cell being connected to column precharge means, the improvement comprising: a. row addressing means; comprised of silicon gate CMOS circuitry operatively connected to the input means of each cell for selecting one row of storage cells; b. column addressing means comprised of silicon gate CMOS circuitry operatively connected to the input means of each cell for selecting one column of cells, the cell proximate to the intersection of the row of selected cells and the column of selected cells being uniquely selected; c. data means, comprised of silicon gate CMOS circuitry operatively connected to the input means and to the output means of each cell for supplying a binary ''''1'''' or a binary ''''0'''' to the uniquely selected cell selectively from the outside data source or from the output means of the cell; and d. feedback refreshing means, comprised of silicon gate CMOS circuitry operatively connected to the data means, for refreshing the binary contents of each cell as controlled by the binary data content of the data means; and e. all said field effect transistors have threshold voltages of less than 1 volt, wherein no diffused guard rings are utilized to block parasitic current paths, wherein no diffused guard rings are utilized to block parasitic current paths, and wherein all field effect transistors have threshold voltages of less than 1 volt.
2. The monolithic memory array of claim 1 further comprising internal clocking means for developing timing signals, operatively connected to at least the column precharge means and the feedback refreshing means, for controlling the internal timing of the monolithic memory array.
3. The monolithic array of claim 2 wherein the row addressing means include: a. i. address inverting buffer means, comprised of CMOS circuitry, for providing internal address and address complement voltages from M row address input terminals; ii. row decoding means, comprising CMOS decode gates, bussing means for transmitting address and address complement signals from the address inverting buffer means to inputs of the CMOS decode gates, whereby each unique voltage configuration of the M row address inputs causes selection of only one of the 2M rows; iii. control bussing means, comprising at least one separate control bus for each row in the memory array operatively connected to each dynamic MOS storage cell in that row, and; iv. row selection means comprised of CMOS circuitry, wherein outputs of the row decoding means are operatively connected to the row selection means, causing the control bussing means of the selected row to be operatively connected to the internal clock means.
4. The monolithic memory array of claim 2 wherein the column decoding means include a CMOS decoding tree.
5. The monolithic memory array of claim 2 wherein the column decoding means and the row decoding include CMOS decoding trees.
6. The monolithic memory array of claim 2 wherein the data means include: c. i. data bussing means, comprising at least one separate data bus for each column in the memory array operatively connected to each storage cell in the subject column, for transmitting binary data to and from the storage cell in the row selected by the row addressing means; ii. column precharge means, comprised of CMOS circuitry for establishing an approriate voltage level on the data bussing menas prior to read, write, and refresh operations; iii. decoded column bussing means for transmitting binary data to and from the uniquely selected storage cell via the data bussing means; iv. column selection and amplifying means, comprised of CMOS circuitry, for selecting one of the 2N columns to allow binary data to be efficiently transmitted between the data bussing means and the decoded column bussing means, and; v. gated data input-output buffer means, comprised of CMOS circuitry, having at least one terminal, connecting the decoded column bussing means to a data terminal when a chip enable input terminal is a logical ''''1'''' level, and disconnecting the decoded column bussing means from the data terminal when the chip enable input is at a logical ''''0,'''' for amplifying output data from the decoded column bussing means to a data terminal receiving output data, and for efficiently transmitting input data from an input data terminal to the decoded column bussing means.
7. The monolithic memory of claim 6 wherein the column addressing means include: b. i. address inverting buffer means, comprised of CMOS circuitry, for providing internal address and address complement voltages from N column address input terminals; ii. column decoding means, comprised of column CMOS decode gates and CMOS circuitry, having bussing means for transmitting address and address complement voltages from the column address inverting buffer means to inputs of the column CMOS decode gates, and having the outputs of the column CMOS decode gates operatively connected to the column selection and amplifying means, whereby each unique voltage configuration of the N-column address input terminals causes selection of only one of the 2N columns.
8. The monolithic memory array of claim 7 wherein each column has separate feedback refreshing means comprising at least one inverting circuit operatively connected to the data bussing means for receiving a voltage level representing the binary data stored in the storage cell of the selected row for the subject column, and for amplifying the voltage level representing the binary data, and for transmitting amplified binary data, in functional timing sequence, to the data input means for transmission to a storage node of the subject storage cell, thereby refreshing the storage node.
9. The monolithic memory array of claim 8, wherein the dynamic MOS storage cell comprises: a. a first N-channel MOS storage transistor having source and drain electrodes, and gate electrode for storing binary data represented by a relatively high or low voltage level; b. a second N-channel MOS read gating transistor having a source electrode connected to the drain electrode of the first MOS storage transistor, a drain electrode connected to a read data bussing line, and a gate electrode connected to a read control bussing line; c. a third N-channel MOS write-refresh gating transistor having a source electrode connected to the gate electrode of the first MOS storage transistor, a drain electrode connected to a write-refresh data bussing line, and a gate electrode connected to a write-refresh control bussing line.
10. The monolithic memory array of claim 9 wherein the internal clocking means comprises: a. a clock bus operatively connected to a clock input terminal and to the data precharge means; b. an upper-half array select circuit having the clock bus as an input, and having as another input an output of a CMOS inverter having as its input a half-array selection address input terminal, the upper half-array select circuit having as outputs an upper-half-array select clock, a delayed upper-half-array select clock, and an upper-half-array refresh amplifier gating clock, and; c. a lower-half-array select circuit having the clock bus as an input, and having as another input the half-array selection address input terminal, the lower half-array select circuit having as outputs a lower-half-array select clock, a delayed lower-half-array select clock, and a lower-half-array refresh amplifier gating clock.
11. The monolithic memory array of claim 10 wherein: a. the new address inverting buffer means comprises M row address CMOS inverters each comprising one P-channel transistor and one N-channel transistor, each CMOS inverter having an input connected to a row address input terminal and an output connected to a row address complement bus; b. the row decoding means comprises 2M CMOS NAND gates each comprising M P-channel transistors in parallel connection and M N-channel transistors in series connection, and also having M input terminals each connected to row address input busses and row address complement busses in such manner that each unique voltage configuration of the M row address inputs causes selection of one and only one of the 2M NAND gates; c. the control bussing means comprises 2M read control busses each operatively connected to the gate electrode of the read gating device of each MOS storage cell of the subject row, and 2M write-refresh control busses each operatively connected to the gate of the write-refresh transistor of each MOS memory cell in the subject row, and; d. the row selection means comprises a separate row select circuit for each row in the upper-half-array and one for each row in the lower-half-array, each upper-half-array row select circuit having connected to one input the output of one of the CMOS NAND decode gates and having connected to a second input having internally derived upper-half-array select clock, and having connected to a third input an internally derived delayed upper-half-array select clock, and having as a first output a read control bus and having as a second output a write-refresh control bus, both operatively connected to one row of the upper-half-array, and each lower-half-array row select circuit having connected to one input the output of one of the CMOS NAND decode gates and having connected to a second input an internally derived lower-half-array select clock, and having connected to a third input an internally derived delayed lower-half-array select clock, and having as a first output a read control bus and having as a second output a write-refResh control bus, both operatively connected to one row of the lower-half-array, each row select circuit comprising a first P-channel transistor, a second P-channel, and a third N-channel transistor in series connection between a VDD supply bus and a VSS supply bus, the first and third transistors having their gate electrodes operatively connected to one of the CMOS NAND decode gate outputs, and the second transistor having its gate output electrode operatively connected to the internally derived upper-half-array select clock.
12. The monolithic memory array of claim 11 wherein: a. the data bussing means comprise one separate write-refresh bus for each entire column of MOS storage cells operatively connected to the write-refresh terminal of each MOS storage cell, and a read bus operatively connected to the read terminal of each MOS storage cell of the subject column in the upper half of the storage array and also operatively connected to a refresh amplifier, and a lower read bus operatively connected to the main terminal of each MOS storage cell in the subject column and the lower half of the array and operatively connected to a lower refresh amplifier; b. the column precharge means comprise a separate P-channel transistor operatively connecting each lower read bus to the VDD supply bus and operatively connecting each upper read bus to the VDD supply bus, and having a precharge clock connected to a gate electrode of said P-channel transistor, and a CMOS inverter having the precharge clock as an input, said CMOS inverter having its output connected to a gate electrode of an N-channel transistor which operatively connects each write-refresh data bus to the VSS supply bus; c. the decoded column bussing means comprises a separate data in bus for transmitting binary data to the uniquely selected column from an input-output buffer circuit and a separate data out complement bus for transmitting binary data from the uniquely selected column to an input-output buffer circuit; d. the column selection and amplifying means comprise a separate 4-transistor CMOS circuit for each column, each circuit having N-channel gating devices with gate terminals connected to the output of a CMOS NOR decode gate, and having an internally generated write enable input operatively connected to the gate electrode of another N-channel transistor, each column selection and amplifying circuit operatively connected to the data in bus and the data out complement bus, and; e. the gated data input-output buffer means comprise a CMOS inverter having a data in terminal as its input and having its output gated to a data input bus by an N-channel transistor having its gate electrode connected to a chip enable input terminal and a data out complement terminal gated via the data out complement bus to a data out complement output terminal by an N-channel transistor having its gate connected to the chip enable input terminal.
13. The monolithic memory of claim 12 wherein: a. the column address inverting buffer means comprise a separate CMOS inverter for each column address input; b. the column decoding means comprise a separate CMOS NOR gate for each column of the storage array, each NOR gate including N P-channel transistors in series connection and N N-channel transistors in parallel connection, and having N inputs, each of the inputs operatively connected to CMOS address inverter outputs and column address inputs whereby each unique voltage configuration of the N address input terminals causes selection of only one of the 2N NOR gates, the output of each NOR gate being connected to a column selection and amplifying circuit.
14. The monolithic memory of claim 13 wherein the feedback refreshing means comprise: a. an upper refresh amplifier and a lower refresh amplifier for each column, each having identical circuit configuration, each having an output terminAl operatively connected to the write-refresh bus of a column, and each refresh amplifier having an input connected, respectively, to the upper read bus and the lower read bus of a column, and each upper refresh amplifier being gated by the upper-half-array refresh amplifier gating clock, and each lower refresh amplifier being gated by the lower-half-array refresh amplifier gating clock; b. each refresh amplifier includes a standard CMOS inverter comprised of a P-channel transistor and an N-channel transistor in series connection, with their common drain electrodes connected to a main electrode of a gating transistor, the refresh amplifier having as an input the connected gate electrodes of the series connected transistors, and having as a clock input the gate electrode of the gating transistor, and having as an output the other main electrode of the gating transistor.
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