Time division switching system
阅读：938发布：2023-05-24
专利汇可以提供Time division switching system专利检索，专利查询，专利分析的服务。并且Control memories actuate space division switching matrices to connect plural time division multiplex lines to different input and output connections of time slot unit storage locations for performing plural time slot interchange functions simultaneously and independently in different portions of the locations. In two embodiments the locations are in a dynamic form as the respective stages of a reentrant shift register and the respective locations in a circulating delay line. In another embodiment the locations are in a static form as the respective memory devices in a random access memory. In any embodiment status and compare circuits evaluate storage location control signals for finding an available path of suitable length in the time-storage domain of the locations for establishing new connections between calling and called lines.，下面是Time division switching system专利的具体信息内容。
1. In combination a plurality of space-divided input signal channels for supplying respective time division multiplex pulse trains each representing a plurality of different signal messages, memory means having a plurality of memory locations for storing a plurality of information signals, each location having storage capacity for only as much signal as is received from a channel in one time slot, input means for selectively coupling any of said channels to respective inputs of different ones of said locations during each time division multiplex time slot and with substantially the same time slot delay imparted to all channels between a channel and a location coupled thereto, a plurality of output time division multiplex space-divided signal channels for receiving time division multiplex signals from said locations, output means for selectively coupling outputs of any of said locations to different ones of said output channels during each time division multiplex time slot and with substantially the same time slot delay imparted to all channels between a channel and a location coupled thereto, and means cooperatively controlling said input and output selective coupling means for time slot interchange coupling between said input and output channels for respective messages in said trains.
2. The combination in accordance with claim 1 in whIch the number of said storage locations is approximately three times the number of said input lines for offered traffic level in said input and output lines of about 0.5 erlang per time slot for a channel.
3. The combination in accordance with claim 1 in which said controlling means includes means for simultaneously actuating in each time slot all of said input coupling means for channels having message signals during such time slot and simultaneously actuating in each time slot all of said output coupling means for channels to receive message signals during such time slot.
4. The combination in accordance with claim 1 in which said memory means comprises a random access memory wherein each storage location is a different one of said memory locations.
5. The combination in accordance with claim 1 in which said controlling means comprises means, responsive to message termination on time slot interchange coupled input and output channels, for identifying said channels and respective time slots utilized for such message, and means for terminating operation of said controlling means for said input and output channels in such time slots.
6. The combination in accordance with claim 1 in which said memory means, input and output signal channels, and input and output coupling means comprise a first set of time slot interchanging apparatus, at least one additional set of time slot interchanging apparatus of the same type as said first set is connected for tandem operation with said first set, wherein one of said output channels of said first set is a time division multiplex link connected to an input channel of said additional set, and said controlling means includes means for controlling said sets of said time slot interchange apparatus to establish said time slot interchange coupling in said first set and thereafter in said additional set for establishing time slot interchange coupling among selected channels served by said sets.
7. The combination in accordance with claim 1 in which said memory means comprises a circulating delay line memory wherein each storage location is a different one of said memory locations, and means for completely circulating said locations through said memory once during each time slot.
8. The combination in accordance with claim 1 in which each of said memory means locations comprises a bistable storage element having set and reset input connections, and said input coupling means comprises a space division selective switching matrix having a first set of rails connected respectively to said input channels and having a second set of rails connected respectively to said input connections of a different one of said storage elements, and gating means operable by said controlling means for interconnecting any rail of said first set to any one of said storage elements, said gating means comprising means for converting single-rail logic signals on rails of said first set to double-rail logic signals on rails of said second set.
9. The combination in accordance with claim 1 in which said controlling means comprises means for identifying calling and called time slots on an input calling line and an output called line, respectively, and means for determining an available time-storage domain sequence among said locations and between said calling and called time slots.
10. The combination in accordance with claim 9 in which said determining means comprises means for determining storage location availability of said locations starting from the time of said calling time slot, means responsive to identification of said called time slot, for halting operation of said availability determining means, and means for registering said location availability from said availability determining means.
11. The combination in accordance with claim 1 in which said memory means comprises a shift register wherein each stage is a different one of said locations.
12. The combination in accordance with claim 11 in which said shift register is provided with a reentrant connection between the output of the last stage and the input of the first stage to form a closed shift register loop.
13. The combination in accordance with claim 1 in which said controlling means includes means for actuating in an input sequence in each time slot all of said input coupling means for channels having message signals during such time slot and actuating in an output sequence all of said output coupling means for channels to receive message signals during such time slot.
14. The combination in accordance with claim 13 in which each of said time slots is subdivided into first and second parts, said input coupling sequence and said output coupling sequence occur in completely different parts of such time slot, and said memory means are provided with a common input connection time shared in said input sequence by said input coupling means and a common output connection which is time shared by said output coupling means during said output sequence.
15. The combination in accordance with claim 1 in which said controlling means comprises means for detecting, for a particular message, a time-location sequence that is available for message transmission coupling and includes available time slots on input and output channels to be interconnected, for a particular message, and means for connecting such input channels to a location and in a time slot defining the start of said sequence and connecting such output channel to a location and in a time slot defining the end of that sequence in every frame of one of said trains including said particular message.
16. The combination in accordance with claim 15 in which said locations are assigned a predetermined sequential relationship to one another, and said detecting means comprises means for identifying for said connecting means only the time-location sequence having the input location of lowest order, among input locations of any available time-location sequence, in said sequential relationship.
17. The combination in accordance with claim 15 in which said detecting means includes means for detecting an output channel available time slot the least time spread with respect to the input channel time slot.
18. The combination in accordance with claim 15 in which said detecting means comprises means for indicating an available calling time slot on an incoming channel, means for indicating an available time slot on a called outgoing channel, means, operative in each time slot, for registering the availability, or unavailability, for message transmission status of each of said locations, means, operative in each time slot, for registering changes in said status, and means for indicating, in response to said status change registering means a portion of said locations that is available during and between said calling and called time slots.
19. The combination in accordance with claim 15 in which said detecting means comprises means for indicating an available calling time slot on an incoming channel, means for indicating an available time slot on a called outgoing channel, means, operative in each time slot, for registering the availability, or unavailability, for message transmission status of each of said locations, means operative in each time slot, for registering changes in said status, and means for indicating in response to said status change registering means one of said locations that is available during and between said calling and called time slots.
20. The combination in accordance with claim 1 in which said controlling means comprises a control memory for each of said channels and each control memory has a word storage location for each time slot of a frame of time division signal transmission, means for storing in said word locations the names of memOry means locations to be coupled to respective ones of said channels during time slots corresponding to said word locations, and means, operative during each time slot, for reading out a different one of said word locations in each of said control memories so that each control memory reads out one word location in each time slot and all control memories are fully read out during a time division frame.
21. The combination in accordance with claim 20 in which said controlling means includes means for applying outputs of all of said control memories to operate said input coupling means simultaneously and to operate said output coupling means simultaneously.
22. The combination in accordance with claim 20 in which said controlling means includes means for scanning outputs of all of said control memories in sequence once during each time slot, and means for actuating one of said coupling means for coupling a channel corresponding to the control memory being read out to a memory means location named in the readout.
23. The combination in accordance with claim 20 in which said controlling means includes means for accessing said memory means locations in a fixed sequence at a rate (R+1) n where R+1 is the number of such locations and n is the number of time slots per frame of time division signal transmission in one of said trains, means for comparing memory means location names read out of said control memories with the name of the memory means location then being accessed and producing a match signal when they are the same, and means responsive to said match signal actuating one of said coupling means for coupling a channel, corresponding to the control memory from which the match signal was produced, to the memory means location then being accessed.
24. The combination in accordance with claim 1 in which said controlling means comprises means for separately establishing time slot interchange coupling in each direction between said input and output channels for any given one of said messages, said coupling for each such direction being independent in a time sense of the coupling in the other direction.
25. The combination in accordance with claim 24 in which each time slot for time division message signal transmission has transmit and receive time slot phases on each of said channels, and said establishing means comprises means for establishing an outgoing time slot interchange coupling from an input to an output channel in any one or more of the time slots of a frame of time division message signal transmission, and means for establishing a return time slot interchange coupling from such output channel to such input channel in any one or more of said time slots of a frame, such return time slots being the same as or different from the outgoing time slots.
26. The combination in accordance with claim 1 in which a plurality of signal lines are provided for transmitting and receiving signals when active, line concentrators are provided for coupling signals on a time division multiplex basis between said channels and active one of said lines, and each of said concentrators includes means for separately determining transmit time slots and receive time slots for active one of said lines coupled thereto.
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