专利汇可以提供Logic chip including embedded magnetic tunnel junctions专利检索,专利查询,专利分析的服务。并且An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.,下面是Logic chip including embedded magnetic tunnel junctions专利的具体信息内容。
What is claimed is:
This application is a §371 national phase of PCT/US2013/32151 filed Jun. 15, 2013, the content of which is hereby incorporated by reference.
Embodiments of the invention are in the field of semiconductor devices and, in particular, logic chips having embedded memory.
Integrating memory directly onto a logic chip (e.g., microprocessor chip) enables wider buses and higher operation speeds compared to having physically separate logic and memory chips. Such memory may include traditional charge-based memory technologies such as dynamic random-access memory (DRAM) and NAND Flash memory.
Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures, in which:
Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. “An embodiment”, “various embodiments” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. “First”, “second”, “third” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and “coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment. Terms such as “upper” and “lower” “above” and “below” may be understood by reference to the illustrated X-Z coordinates, and terms such as “adjacent” may be understood by reference to X-Y coordinates or to non-Z coordinates.
As stated above, integrating memory directly onto a logic chip has advantages. Such memory may include DRAM and NAND Flash memory. However, DRAM and NAND Flash memory have scalability issues related to increasingly precise charge placement and sensing requirements, and hence embedding charge-based memory directly onto a high performance logic chip is problematic at, for example, sub-20 nm technology nodes.
An embodiment includes a logic chip integrated with a memory; however the memory scales to smaller geometries than possible with traditional charge-based memories. In one embodiment the memory is a spin-torque transfer magnetoresistive random access memory (STT-M RAM), which relies on resistivity rather than charge as the information carrier. More specifically, an embodiment includes at least one STT-MRAM memory embedded within a memory layer of a logic chip (e.g., processor). The at least one STT-MRAM memory may include at least one STT-MRAM array having at least one magnetic tunnel junction (MTJ). Other memories besides STT-MRAM, such as resistive RAM (RRAM), are used in other embodiments.
An embodiment integrates a STT-MRAM within a logic chip, where the memory includes a MTJ that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.
For clarity purposes some details are not labeled in
In the embodiment of
In an embodiment there is horizontal separation between the edges of hardmask 130 and top MTJ 125 films compared to the edges of tunnel barrier 135 and bottom MTJ 140 films. This horizontal separation provides a margin with respect to top MTJ-to-bottom MTJ shorting.
An embodiment includes remnants of etch-stop film 115 on the edges of tunnel barrier 135 and bottom MTJ 140 films. Film 115 protects tunnel barrier film 135 and bottom MTJ films 140 from sidewall oxidation and/or corrosion.
An embodiment retains the same regular low-k ILD material 155, 170, 185 in logic area 105 (e.g., processor) and memory layer 110 that includes embedded MTJs. Doing so helps the embodiment meet stringent RC delay requirements of modern high performance logic chips. However, area 110 also includes flowable oxide layer 145, which provides an ILD not found in area 105 (or at least portions of area 105).
In
In
In
In one embodiment the processes corresponding to
In
In
In
In
The process then produces the device included in
Another embodiment utilizes a different process and end product. The process and embodiments of
Next, a resist layer is applied and patterned to mask off logic circuit area 105 from area 110 where MTJs are located. The exposed hardmask layer is etched, stopping on the low-k ILD film, and then the exposed low-k ILD material is etched, stopping on the underlying etch-stop film (layer 175). The hardmask and low-k ILD films are etched using, for example, dry etch process techniques. Then the resist residue is removed.
Afterwards, the wafer surface is covered with a flowable oxide material (material 145), which fills the gaps in between the MTJs. Flowable oxide overburden is then removed using, for example, an oxide CMP process that selectively stops on the underlying etch-stop material which was formed at the beginning of this alternative method. The flowable oxide material remains inside the gaps in between the MTJs.
Next the exposed etch-stop material is removed using, for example, a wet or dry etch process (depending on the film composition). Additional low-k ILD material is deposited onto the wafer, such that the total low-k ILD thickness is built up to the value desired for forming the regular interconnect structures in the logic circuit area (area 105). This value is highly variable and depends on, for example, which metal layer the MTJs are integrated into. In one embodiment, the total low-k ILD thickness may be between 30-750 nm, including 50, 100, 200, 300, 400, 500, 600, 700 nm thicknesses. Trenches and via openings are then fabricated into the low-k ILD material using, for example, dual damascene patterning and etching techniques. Copper interconnect structures are then formed inside the trenches and via openings using, for example, dual damascene barrier/seed deposition, copper electroplating, and copper CMP processes. Subsequent copper interconnect layer(s) are formed, as desired, using dual damascene process techniques.
Although the alternate embodiment has more total process steps compared to the embodiment of
In an embodiment an incoming wafer may include patterned copper interconnects fabricated using standard copper damascene processing (e.g.,
Accordingly, various processes have been addressed above, any of which may result in the embodiment of
Various embodiments (e.g.,
Various embodiments (e.g.,
Various embodiments (e.g.,
Various embodiments (e.g.,
Embodiments may have various combinations such as any combination of the immediately aforementioned elements (a), (b), (c), and/or (d).
As used herein a layer may have sublayers. For example, a top MTJ layer may actually be composed of many sublayers. For example and as explained above, in one embodiment MTJ film 140 consists of (from bottom to top) 3 nm tantalum (Ta); 20 nm platinum manganese (PtMn); 2.3 nm cobalt iron (Co70Fe30); 0.8 nm Ruthenium (Ru); 2.5 nm cobalt iron boron (Co60Fe20B20). Thus, 5 sublayers are included in MTJ film 140. Tunnel barrier 135 includes 1.2 nm magnesium oxide (MgO) but in alternative embodiments layer 135 may include one or more sublayers. Top MTJ 125 film includes 2.5 nm Co60Fe20B20 but in alternative embodiments the layer may include one or more sublayers. Hardmask 130 material includes 50 nm Ta but in alternative embodiments the layer may include tantalum nitride, titanium and titanium nitride and/or one or more sublayers. For example, an embodiment may include a top MTJ film with sublayers (1.7 nm Co60Fe20B20/5 nm Ta/5 nm Ru), a tunnel barrier (0.85 nm MgO), and a bottom MTJ film with sublayers (5 nm Ta/1 nm Co60Fe20B20). Another embodiment may include a top MTJ film with sublayers (1.0-1.7 nm Co60Fe20B20/5 nm Ta/5 nm Ru), a tunnel barrier (0.85-0.9 nm MgO), and a bottom MTJ film with sublayers (5 nm Ta/10 nm Ru/5 nm Ta/1.0-1.3 nm Co60Fe20B20). Another embodiment may include a top MTJ film with sublayers (CoFeB), a tunnel barrier (MgO), and a bottom MTJ film with sublayers (PtMn/CoFe/Ru/CoFeB). Another embodiment may include a top MTJ film with sublayers (CoFeB(3 nm)/Ru(7 nm)/Cu(110 nm)/Ru(2 nm)/Ta(10 nm) or CoFeB(3 nm)/Ta(8 nm)/Ru(7 nm)), a tunnel barrier with sublayers (Mg(0.4 nm)+MgO(0.6 nm)), and a bottom MTJ film with sublayers (Ta(5 nm)/CuN(20 nm)/Ta(10 nm)/PtMn(15 nm)/CoFe(2.5 nm)/Ru(0.8 nm)/CoFeB(3 nm)). Many other examples are possible and understood to those of ordinary skill in the art and are not described herein for purposes of brevity.
Embodiments may be used in many different types of systems. For example, in one embodiment a communication device (e.g., cell phone, Smartphone, netbook, notebook, personal computer, watch, camera) can be arranged to include various embodiments described herein. Referring now to
Notably, at times herein “top MTJ” and “bottom MTJ” layers are used for purposes of explanation, however, a MTJ can be “inverted” making the top layer into the bottom layer (i.e., changing the viewing perspective) without deviating from innovative concepts of embodiments described herein.
As a further example, at least one machine readable medium comprises a plurality of instructions that in response to being executed on a computing device, cause the computing device to carry out any of the methods described herein. An apparatus for processing instructions may be configured to perform the method of any of the methods described herein. And an apparatus may further include means for performing any of the methods described herein.
Embodiments may be implemented in code and may be stored on a machine readable storage medium having stored thereon instructions which can be used to program a system to perform the instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
The following examples pertain to further embodiments.
Example 1 includes an apparatus comprising: a monolithic substrate; a memory area, comprising a magnetic tunnel junction (MTJ) that includes a tunnel barrier directly contacting lower and upper MTJ layers, located on the substrate; and a logic area located on the substrate; wherein a horizontal plane, which is parallel to the tunnel barrier, intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another; wherein the first and second ILDs directly contact one another.
In Example 2, the subject matter of Examples 1 can optionally include wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer sidewall by a horizontal offset space that defines a horizontal offset distance.
In Example 3, the subject matter of Examples 1-2 can optionally include a spacer, having a width equal to the horizontal offset distance, directly contacting the upper MTJ layer and the tunnel barrier.
In Example 4, the subject matter of Examples 1-3 can optionally include a hardmask directly contacting an upper surface of the upper MTJ layer and the spacer.
In Example 5, the subject matter of Examples 1-4 can optionally include wherein the horizontal plane intersects etch stop material included between the MTJ and the first ILD material; and the etch stop material is included in an etch stop layer that directly contacts the hardmask.
In Example 6, the subject matter of Examples 1-5 can optionally include wherein the horizontal plane intersects etch stop material included between the MTJ and the first ILD material; and the etch stop material is included in an etch stop layer that directly contacts an upper surface of the spacer.
In Example 7, the subject matter of Examples 1-6 can optionally include wherein the horizontal plane intersects etch stop material included between the MTJ and the first ILD material.
In Example 8, the subject matter of Examples 1-6 can optionally include wherein the etch stop material directly contacts at least one of the tunnel barrier and the lower MTJ layer.
In Example 9, the subject matter of Examples 1-8 can optionally include wherein the etch stop material is included in an etch stop layer having directly connected horizontal and vertical lengths that both directly contact the first ILD.
In Example 10, the subject matter of Examples 1-9 can optionally include wherein the etch stop material is included in an etch stop layer extends from the memory area to the logic area.
In Example 11, the subject matter of Examples 1-10 can optionally include wherein: the first ILD material includes at least one of silicon oxide, silicon oxynitride, porous silicon oxide, fluorinated silicon oxide, carbon-doped oxide, porous carbon-doped oxide, polyimide, polynorbornene, benzocyclobutene, flowable oxide, and polytetrafluoroethylene and the second ILD material includes an additional at least one of silicon oxide, silicon oxynitride, porous silicon oxide, fluorinated silicon oxide, carbon-doped oxide, porous carbon-doped oxide, polyimide, polynorbornene, benzocyclobutene, flowable oxide, and polytetrafluoroethylene; and the first bottom MTJ includes sublayers comprising at least two of tantalum, platinum manganese; cobalt iron; Ruthenium (Ru); and cobalt iron boron.
In Example 12, the subject matter of Examples 1-11 can optionally include wherein the logic area is included in a processor and the memory is spin torque transfer magnetoresistive random access memory (STT-MRAM).
In Example 13, the subject matter of Examples 1-12 can optionally include wherein at least one of the first upper MTJ layer, first lower MTJ layer, and first tunnel barrier includes sublayers.
In Example 14, the subject matter of Examples 1-13 can optionally include the memory area comprises an additional MTJ, having a additional tunnel barrier directly contacting additional lower and upper MTJ layers, located on the substrate; and the horizontal plane intersects the additional MTJ; a contiguous etch stop portion directly contacts both the MTJ and the additional MTJ.
In Example 15, the subject matter of Examples 1-14 can optionally include wherein the contiguous etch stop portion directly contacts the first ILD.
Example 16 includes a method comprising: forming a memory area, comprising a magnetic tunnel junction (MTJ) that includes a tunnel barrier directly contacting lower and upper MTJ layers, on a monolithic substrate; and forming a logic area located on the substrate; wherein a horizontal plane, which is parallel to the tunnel barrier, intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another.
In Example 17, the subject matter of Example 16 can optionally include forming a sidewall of the upper MTJ layer horizontally offset a horizontal offset distance from a sidewall of the lower MTJ layer.
In Example 18, the subject matter of Examples 16-17 can optionally include forming a hardmask directly contacting an upper surface of the upper MTJ layer; and forming a spacer, having a width equal to the horizontal offset distance, in direct contact with the upper MTJ layer and the hardmask.
In Example 19, the subject matter of Examples 16-18 can optionally include forming a spacer, having a width equal to the horizontal offset distance, in direct contact with the upper MTJ layer and the tunnel barrier.
In Example 20, the subject matter of Examples 16-19 can optionally include forming an etch stop layer directly contacting the MTJ and forming the first ILD in direct contact with the etch stop; forming the second ILD in direct contact with the first ILD and the etch stop; and polishing the second ILD while the second ILD is in direct contact with the first ILD.
In Example 21, the subject matter of Examples 16-20 can optionally include forming an etch stop layer directly contacting the MTJ and forming the second ILD in direct contact with the etch stop; forming the first ILD in direct contact with the second ILD and the etch stop; and polishing the first ILD while the first ILD is in direct contact with the second ILD.
Example 22 includes an apparatus comprising: a first magnetic tunnel junction (MTJ) including a first upper MTJ layer, a first lower MTJ layer, and a first tunnel barrier directly contacting a first lower surface of the first upper MTJ layer and a first upper surface of the first lower MTJ layer; a memory area, including the first MTJ, and a logic area form on a monolithic substrate; wherein the first upper MTJ layer includes a first upper MTJ layer sidewall and the first lower MTJ layer includes a first lower MTJ sidewall horizontally offset from the first upper MTJ layer sidewall by a first horizontal offset space that defines a first horizontal offset distance; wherein a first spacer, having a width equal to the first horizontal offset distance, directly contacts the first upper MTJ layer and the first tunnel barrier; wherein a first horizontal plane, parallel to the first lower surface of the first upper MTJ layer, intersects the first MTJ, a first ILD material adjacent the first MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another.
In Example 23, the subject matter of Example 22 can optionally include wherein the first horizontal plane intersects a first polish stop material included between the first MTJ and the first ILD material.
In Example 24, the subject matter of Examples 22-23 can optionally include a first hardmask directly contacting a first upper surface of the first upper MTJ layer and the first spacer.
In Example 25, the subject matter of Examples 22-24 can optionally include wherein the first ILD material includes flowable oxide and the second ILD material includes at least one of silicon oxide, porous silicon oxide, fluorinated silicon oxide, carbon-doped oxide, porous carbon-doped oxide, polyimide, polynorbornene, benzocyclobutene, and polytetrafluoroethylene.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
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