Address development technique utilizing a content addressable memory
阅读：729发布：2022-03-19
专利汇可以提供Address development technique utilizing a content addressable memory专利检索，专利查询，专利分析的服务。并且A content addressable memory is disclosed which provides for fast address development in a relatively addressed data processing system. The content addressable memory includes an associative memory, an encoder and a buffer memory. If the address provided to the associative memory had been previously stored in the associative memory, a signal is generated to the encoder which enables the actual address to be read from the buffer memory. If the address is not contained in the associative memory, actual address development through main memory is made. Additional features included in the content addressable memory are a replacement logic for indicating the next replaceable location in the associative memory and selection logic for determining the locations in the associative memory to be accessed.，下面是Address development technique utilizing a content addressable memory专利的具体信息内容。
1. An apparatus for developing a relative address for a memory having variable sized segments, said apparatus comprising: means for storing a plurality of first addresses, and second addresses means for comparing a second address with said plurality of first addresses, encoder means, responsive to said comparing means, for providing a third address when said second address is found matched to one of said plurality of first addresses, and memory means for storing a plurality of fourth addresses, said memory means enabled by said third address from said encoder means to deliver one of said plurality of fourth addresses, said fourth addrss identifying the address of a segment in said segmented memory.
2. An apparatus as defined in claim 1 and further including: no match means responsive to said comparing means when said second address is found not matched to one of said plurality of first addresses, said no match means providing a signal, and selection means for addressing said storing means, said selection means in response to said comparing means identifying one of said pluraliy of first addresses in said storing means.
3. An apparatus as defined in claiM 2 wherein said selection means includes: replacement means for identifying one of said addresses in said plurality of first addresses, said replacement means responsive to said no match means, and logic means for addressing said plurality of first addresses, said logic means responsive to either said replacement means when said second address is not matched or to said comparing means when said second address is matched to one of said plurality of first addresses.
4. An apparatus as defined in claim 3 and further including: means for changing said replacement means when said signal from said no match means is received, said replacement means comprising means to identify to said logic means said replaceable address is said plurality of first addresses, and wherein said logic means identifies said replaceable address in said plurality of first addresses when said comparing means does not indicate a match between said second address and one of said plurality of first addresses.
5. An apparatus as defined in claim 4 wherein said changing means in response to a selected first address reenables said replacement means such that said logic means does not address said selected first address for replacement.
6. An apparatus for developing a relative address for a memory having variable sized segments, said apparatus comprising: means for receiving a first address which directs access to a segment located in said segmented memory, first means for appending a first identifier to an address, said first identifier indicating a valid address, means for storing a plurality of second addresses, each of which may include said first identifier of a valid address, means for comparing said first address and said first identifier of a valid address with said plurality of second addresses, match means responsive to said comparing means for generating a first signal when said first address and said first identifier of a valid address are contained in said plurality of second addresses, and means for identifying the starting address of said segment directed to by said first address, said identifying means including a plurality of third addresses each of which corresponds to one of said plurality of second addresses, said identifying means in response to said first signal selecting one of said plurality of third addresses.
7. An apparatus as defined in claim 6 wherein said selected first address includes a procedure bit identifying the active procedure being excecuted.
8. An apparatus as defined in claim 6 and further including: selection means for addressing said plurality of second addresses, said selection means responsvie to said first signal, and no match means responsive to said comparing means for generating a second signal when said first address and said first identifier of a valid address are not contained in said plurality of second address, said second signal also provided to said selection means.
9. An apparatus as defined in claim 8 and further including: second means for appending a second identifier to an address, said second identifier indicating an active procedure being executed said storing means containing said second identifier of said active procedure among said plurality of second addresses, and means for sensing said second identifier of said active procedure from said storing means, said sensing means providing a third signal to said selection means when said second identifier of said active procedure is sensed, said selection means ensuring that said address of said second identifier of said active procedure in said plurality of second addresses is not destroyed.
10. An apparatus as defined in claim 9 wherein said selection means include: replacement means responsive to said second signal and said third signal for identifying one of said plurality of second addresses, said second signal and said third signal changing said replacement means, and a plurality of logic means for Addressing said plurality of second addresses, each of said logic means addressing one of said plurality of second addresses.
11. An apparatus as defined in claim 10 wherein said logic means includes: said second means for appending said second identifier of said active procedure to one of said plurality of second addresses, said second means responsive to said first signal and to a write active procedure microcommand, means for reading one of said plurality of second addresses, said reading means responsive to said third signal, to said replacement means and to a read microcommand, means for writing said first address into said storing means, said writing means responsive to said third signal, to said replacement means and to a write microcommand, first means for purging said first identifier of a valid address, and second means for purging said second identifier of said active procedure.
12. An apparatus as defined in claim 11 wherein said identifying means includes: encoder means for providing a fourth signal, said encoder means responsive to said first signal, and memory means for storing said plurality of third addresses, said memory means responsive to said fourth signal such that one of said plurality of third addresses is provided, said one of said plurality of third addresses identifying said starting address of said segment directed to by said first address.
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