Storage control and address translation
阅读：799发布：2022-03-22
专利汇可以提供Storage control and address translation专利检索，专利查询，专利分析的服务。并且A virtual memory system comprising a main storage and a smaller high speed buffer. Current virtual-to-real address translations for both the main storage and the buffer are retained in a Storage Control and Address Translator (SCAT). The SCAT comprises a content addressable (associative) memory. The CPU-provided virtual address is used to interrogate the SCAT. If the data that is referenced by the virtual address is available in main storage, the SCAT will provide the main storage real address. If the data is also available in the buffer, the SCAT will provide the buffer real address.，下面是Storage control and address translation专利的具体信息内容。
1. In a data processing system which contains a central processing unit, a main storage having n addressable locations each addressable by a real main storage address, a main storage address register, a buffer storage having fewer than n addressable locations each addressable by a real buffer storage address, a buffer storage address register, addressing means providing virtual addresses, and means for translating virtual addresses to real main storage and real buffer storage addresses, wherein each of said virtual addresses comprises a main storage virtual address, a buffer storage virtual address, a main storage real address portion and a buffer storage real address portion; an improved storage control and addressing means comprising: an associative memory comprising a plurality of words each of which contains a first interrogation field holding a main storage virtual address; a second interrogation field holding a buffer storage virtual address; a first result field holding the high-order bits of a main storage real address which corresponds to the main storage virtual address that is in said first interrogation field; and a second result field holding the high-order bits of a buffer storage real address which corresponds to the buffer storage virtual address that is in said second interrogation field; first means connected between said addressing means and said associative memory for transmitting said main storage virtual address to said associative memory, said main storage virtual address being subjected in said associative memory to a first comparison with the contents of said first interrogation field of said associative memory; second means connected between said addressing means and said associative memory for transmitting said buffer storage virtual address to said associative memory, said buffer storage virtual address being subjected in said associative memory to a second comparison with the contents of said second interrogation field of said associative memory; both of said comparisons occurring substantially simultaneously; said associative memory containing means responsive to an equal compare on said first comparison to cause a first readout of said first result field from a word in the associative memory in which the first interrogation field was equal to said main storage virtual address; said associative memory containing means responsive to an equal compare on said second comparison to cause a second readout of said second result field from a word in the associative memory in which the second interrogation field was equal to said buffer storage virtual address; means jointly responsive to the occurrence of bOth said first and second readouts to indicate that the data referenced by said addressing means is available in said buffer storage; and means jointly responsive to the occurrence of said first readout and the lack of said second readout to indicate that the data referenced by said addressing means is available in said main storage and is not available in said buffer storage.
2. The storage control and addressing means of claim 1 further comprising: third means connected between said associative memory and said main storage address register to transmit the high-order bits of a main storage real address from said first result field to said main storage address register after said first readout; and fourth means connected between said associative memory and said buffer storage address register to transmit the high-order bits of a buffer storage real address from said second result field to said buffer storage address register after said second readout.
3. The storage control and addressing means of claim 2 wherein: said associative memory comprises a first associative memory containing said first interrogation field and said first result field, and a second associative memory containing said second interrogation field and said second result field; said first means is connected between said addressing means and said first associative memory; said second means is connected between said addressing means and said second associative memory; said third means is connected between said first associative memory and said main storage address register; and said fourth means is connected between said second associative memory and said buffer storage address register.
4. The storage control and addressing means of claim 3 wherein said associative memory further comprises: a single entry register for receiving said main storage virtual address and said buffer storage virtual address from said central processing unit; first gating means connected between said entry register and said first associative memory for transmitting said main storage virtual address to said first associative memory for said first comparison; and second gating means connected between said entry register and said second associative memory for transmitting said buffer storage virtual address to said second associative memory for said second comparison.
5. The storage control and addressing means of claim 1 wherein: said associative memory comprises a first associative memory containing said first interrogation field and said first result field, and a second associative memory containing said second interrogation field and said second result field; said first means is connected between said addressing means and said first associative memory; and said second means is connected between said addressing means and said second associative memory.
6. The storage control and addressing means of claim 5 wherein said associative memory further comprises: a single entry register for receiving said main storage virtual address and said buffer storage virtual address from said central processing unit; first masking means connected between said entry register and said first associative memory for transmitting said main storage virtual address to said first associative memory for said first comparison; and second masking means connected between said entry register and said second associative memory for transmitting said buffer storage virtual address to said second associative memory for said second comparison.
7. In a virtual storage system in which the virtual storage is divided into a predetermined number of pages with each page consisting of a plurality of blocks of data, a main storage for randomly storing page portions of said virtual storage, a buffer storage for storing block portions of said virtual storage, addressing means providing virtual address signals, with each virtual address having a page portion and a block portion; an improved storage control and addressing means comprising: an associative storage comprising a plurality of words each of which contains a virtual address part consisting of a page portion and a block portion, and a first associated real page address portion for addressing said main storage and a second associated real block address portion for addressing said buffer storage; means for simultaneously comparing the page portion of said address signals with corresponding portions of said words in said associative storage and comparing said block portion with corresponding portions of said words in said associative storage to produce a first signal resulting from equality of said first mentioned comparison and a second signal resulting from equality of said second mentioned comparison, said first signal indicating the availability in said main storage of an addressed page portion and said second signal indicating the availability in said buffer storage of an addressed block portion.
8. The storage control and addressing means of claim 7 further including: means responsive to said second signal for transferring said associated real block address to said buffer storage for subsequent use in addressing said buffer storage.
| 标题 | 发布/更新时间 | 阅读量 |
|---|---|---|
| 基于Inter-MAC层的家庭网络融合方法及装置 | 2020-05-13 | 773 |
| 错误检测和纠正电路 | 2020-05-14 | 762 |
| 一种在网络级采用硬件实现共识验证的方法 | 2020-05-08 | 699 |
| 在利用C-DRX的SPS配置的VoLTE中提供功率节省的装置、方法和计算机程序产品 | 2020-05-13 | 263 |
| 用于多媒体回放中的环境信号的分布式同步控制系统 | 2020-05-13 | 120 |
| 基于APB总线的OWI通讯设备 | 2020-05-08 | 503 |
| 文本寻址的方法及装置、介质和电子设备 | 2020-05-08 | 953 |
| 具有自旋轨道转矩设备的内容可寻址存储器 | 2020-05-11 | 668 |
| 用于优化和模拟网页排序和流量的系统和方法 | 2020-05-12 | 39 |
| 数据包的传输方法和装置、存储介质、电子装置 | 2020-05-14 | 344 |
高效检索全球专利专利汇是专利免费检索,专利查询,专利分析-国家发明专利查询检索分析平台，是提供专利分析，专利查询，专利检索等数据服务功能的知识产权数据服务商。
我们的产品包含105个国家的1.26亿组数据，免费查、免费专利分析。
分析报告
专利汇分析报告产品可以对行业情报数据进行梳理分析，涉及维度包括行业专利基本状况分析、地域分析、技术分析、发明人分析、申请人分析、专利权人分析、失效分析、核心专利分析、法律分析、研发重点分析、企业专利处境分析、技术处境分析、专利寿命分析、企业定位分析、引证分析等超过60个分析角度，系统通过AI智能系统对图表进行解读，只需1分钟，一键生成行业专利分析报告。
内容可寻址存储器热门专利
QQ群二维码
意见反馈
意见反馈