Program sequence control
阅读：677发布：2022-03-25
专利汇可以提供Program sequence control专利检索，专利查询，专利分析的服务。并且Program sequence control is described in connection with a computer having a main system program and one or more micro-order programs. The instructions in the system program are of two types: one type actually comprises a micro-order, and the other type designates an address where a sequence of micro-orders begins in a micro-order program. The sequence controller is able to load single micro-order instructions directly into its microorder register for execution, or alternatively it addresses the micro-program to fetch a sequence of micro-orders which correspond to a multiple micro-order instruction. A special type of multiple micro-order instruction requires repetition of a particular micro-order any number of times up to a predetermined maximum. The system employs a single marked bit to distinguish single and multiple micro-order instructions, and also to identify the last micro-order in any multiple micro-order instruction, including the last repetition of a repeat cycle. A buffer register is also provided which permits more rapid access to the main system program through a ''''look ahead'''' feature, and provision is made for discarding the content of the buffer register when the ''''look ahead'''' assumption is invalidated by subsequent program contingencies. Provision is made for delaying the micro-program memory cycle when necessary to allow the system program memory to catch up.，下面是Program sequence control专利的具体信息内容。
1. A program sequence controller comprising: a program memory for simultaneously storing at least one instruction which comprises a single micro-order and at least one instruction which designates at least the first one of a series of micro-order addresses, a micro-program memory for storing micro-orders at said addresses, means for addressing said micro-program memory, means for loading the contents of said program memory into said micro-program addressing means, a micro-order register for storing a micro-order to be executed, means to determine if the outPut of said micro-program addressing means is a micro-order or an address, and means responsive to said determining means to load the output of said micro-program addressing means into said micro-order register when said output is a micro-order and to load the contents of the addressed location in said micro-program memory into said micro-order register when said output is an address.
2. The controller of claim 1 further comprising: a program counter, and incrementing means for said program counter operating in response to at least one predetermined bit in a micro-order fetched from said micro-program memory and also in response to said same predetermined bit in an address issuing from said micro-program addressing means.
3. The controller of claim 2 wherein said determining means responds to said same predetermined bit in said output of said micro-program addressing means to load said output into said micro-order register.
4. A program sequence controller comprising: a program memory, a buffer register loadable from said program memory, micro-program addressing means loadable from said buffer register, a micro-program memory addressable thereby, and means for loading said buffer register from said program memory when said micro-program addressing means is loaded from said buffer register.
5. The controller of claim 4, for use with controlled equipment, and further comprising: means responsive to at least one predetermined condition of said controlled equipment to set said micro-program addressing means to a predetermined address, said micro-program memory storing at said predetermined address a micro-order which has no-operation significance to said controlled equipment.
6. The controller of claim 5 including means for indicating a requirement to replace said reloaded contents of said buffer register before the next loading of said micro-program addressing means; and wherein said predetermined condition is an output from said indicating means.
7. The controller of claim 5 further comprising a program counter for addressing said program memory and means for incrementing said program counter and operating in response to at least one predetermined bit in a micro-order fetched from said micro-program memory, said no-operation micro-order having said predetermined bit.
8. A program sequence controller comprising: a program memory, micro-program addressing means, means for loading said addressing means from said program memory, a micro-program memory addressed by said micro-program addressing means, said micro-program memory being faster than said program memory, means having an output for clocking the loading of said micro-program addressing means, means for controlling the operation of said means having a clocking output, and means responsive to said program memory to detect when said program memory is unavailable and effective then to disable said clock output controlling means.
9. The controller of claim 8 further comprising a micro-order register loadable from said micro-program memory in response to said controlled clock output.
10. A program sequence controller comprising a program counter, a program memory addressable from said program counter, a micro-program counter, means for loading said micro-program counter from said program memory, a micro-program memory addressable from said micro-program counter, a micro-order register loadable from said micro-program memory, means for preventing the loading of said micro-order register, said micro-program memory having repeat micro-orders stored at each one of a stack of n consecutive addresses having a terminal end, repeat micro-order decoding means responsive to the output of said micro-program memory and connected to activate said load preventing means in order to retain the contents of said micro-order register for an additional load cycle thereof each time one of said repeat micro-orders is decoded thereby, said program memory storing at least one repeat instrUction which calls for r repetitions of a preceding instruction, where r is in the range 1 through n inclusive and said repeat instruction designates an address in said micro-program memory which is r steps from said terminal end of said repeat stack, means for stepping said micro-program counter after each micro-program memory fetch whereby to select addresses successively closer to said terminal end of said repeat stack, and means responsive to said micro-program memory for detecting the micro-order at said terminal end of said repeat stack and then incrementing said program counter.
11. The controller of claim 10 wherein said program memory also stores at least one additional instruction which designates a plurality of micro-orders, further comprising means for detecting at least one predetermined bit in a micro-order fetched from said micro-program memory, and wherein said program counter incrementing means operates in response to detection of said predetermined bit, the repeat micro-orders at addresses other than said terminal end do not have said predetermined bit and the repeat micro-order at said terminal end does.
12. The controller of claim 11 wherein said program memory simultaneously stores at least one instruction which comprises a single micro-order and at least one instruction which designates at least one micro-program address, and further comprising means for detecting said same predetermined bit in the output of said micro-program counter in order to determine if said output is a micro-order or an address, and means responsive to said counter output detecting means to load the output of said micro-program counter into said micro-order register when said counter output has said same predetermined bit and to load the contents of the addressed location in said micro-program memory into said micro-order register when said counter output does not have said predetermined bit.
13. A method of controlling a program sequence comprising the steps of: utilizing a program including at least one instruction which comprises at least one micro-order and at least one instruction which designates at least the first one of a series of micro-order addresses which contain micro-orders, determining if an instruction is a micro-order or an address, executing said instruction when it is a micro-order, and using said instruction for selecting at least said one micro-order address and executing the contents of said address when said instruction designates such address.
14. The method of claim 13 further comprising the steps of: maintaining a program count, using said count to address said program, and incrementing said program count when there is a predetermined bit in a micro-order fetched either from said program or from one of said series of micro-order addresses.
15. The method of claim 14 wherein said step of determining if said instruction is a micro-order or an address is accomplished by sampling said same predetermined bit.
16. A method of controlling a program sequence comprising the steps of: utilizing a program and a micro-program, addressing said program, holding the addressed contents of said program in buffer storage, and using the previous contents of said buffer storage for addressing said micro-program.
17. The method of claim 16 further comprising the steps of: using said method to control equipment which recognizes a no-operation micro-order, recognizing at least one predetermined condition of said equipment, having a no-operation micro-order at a predetermined micro-program address, and fetching said no-operation micro-order from said predetermined address and using it to idle said controlled equipment when said predetermined condition is recognized.
18. The method of claim 17 including the steps of detecting a selected predetermined condition; and replacing the contents of said buffer storage before the next micro-program fetch in response to the detection of said predetermined condition.
19. The method of claim 17 wherein said no-operation micro-order has at least one predetermined bit, and further comprising the steps of maintaining a program count, using said program count to address said program, and incrementing said program count whenever a micro-order fetched from said micro-program has said predetermined bit.
20. The method of controlling a program sequence comprising the steps of: utilizing a program, maintaining a micro-program count, taking said micro-program count from- said program at selected time intervals, utilizing a micro-program, addressing said micro-program from said micro-program count, detecting when said program is unavailable to change said micro-program count, and then skipping at least one of said micro-program count change intervals.
21. The method of claim 20 normally comprising the additional step of addressing said micro-program at said same time intervals, but in which said micro-program addressing step is skipped whenever said micro-program count change is skipped.
22. A method of controlling a program sequence comprising the steps of: maintaining a program count, utilizing a program, addressing said program from said program count, maintaining a micro-program count, taking said micro-program count from said program, utilizing a micro-program, addressing said micro-program from said micro-program count, executing a micro-order fetched from said micro-program, storing repeat micro-orders in said micro-program at each one of a stack of n consecutive addresses having a terminal end, recognizing repeat micro-orders fetched from said micro-program, re-executing the previously executed micro-order each time a repeat micro-order is recognized, storing in said program at least one repeat instruction which calls for r repetitions of a preceding instruction where r is in the range 1 through n inclusive and said repeat instruction designates an address in said micro-program which is r steps from said terminal end of said repeat stack, stepping said micro-program count after each micro-program fetch whereby to select addresses successively closer to said terminal end of said repeat stack, recognizing the micro-order at said terminal end of said repeat stack, and incrementing said program count when said terminal end micro-order is fetched.
23. The method of claim 22 wherein said program also contains at least one additional instruction which designates a plurality of micro-orders, including the step of incrementing said micro-program count when there is at least one predetermined bit in a micro-order fetched from said micro-program, the repeat micro-orders at addresses other than said terminal end not having said predetermined bit, and the repeat micro-order at said terminal end having said predetermined bit.
24. The method of claim 23 wherein said program simultaneously contains at least one instruction which comprises a single micro-order and at least one instruction which designates at least one micro-program address, and further comprising the steps of: sampling said same predetermined bit in said micro-program count in order to determine if said output is a micro-order or an address, executing said micro-program count when said count has said same predetermined bit, and executing the contents of the micro-program address designated by said micro-program count when said count does not have said predetermined bit.
| 标题 | 发布/更新时间 | 阅读量 |
|---|---|---|
| 基于Inter-MAC层的家庭网络融合方法及装置 | 2020-05-13 | 773 |
| 错误检测和纠正电路 | 2020-05-14 | 762 |
| 一种在网络级采用硬件实现共识验证的方法 | 2020-05-08 | 699 |
| 在利用C-DRX的SPS配置的VoLTE中提供功率节省的装置、方法和计算机程序产品 | 2020-05-13 | 263 |
| 用于多媒体回放中的环境信号的分布式同步控制系统 | 2020-05-13 | 120 |
| 基于APB总线的OWI通讯设备 | 2020-05-08 | 503 |
| 文本寻址的方法及装置、介质和电子设备 | 2020-05-08 | 953 |
| 具有自旋轨道转矩设备的内容可寻址存储器 | 2020-05-11 | 668 |
| 用于优化和模拟网页排序和流量的系统和方法 | 2020-05-12 | 39 |
| 数据包的传输方法和装置、存储介质、电子装置 | 2020-05-14 | 344 |
高效检索全球专利专利汇是专利免费检索,专利查询,专利分析-国家发明专利查询检索分析平台，是提供专利分析，专利查询，专利检索等数据服务功能的知识产权数据服务商。
我们的产品包含105个国家的1.26亿组数据，免费查、免费专利分析。
分析报告
专利汇分析报告产品可以对行业情报数据进行梳理分析，涉及维度包括行业专利基本状况分析、地域分析、技术分析、发明人分析、申请人分析、专利权人分析、失效分析、核心专利分析、法律分析、研发重点分析、企业专利处境分析、技术处境分析、专利寿命分析、企业定位分析、引证分析等超过60个分析角度，系统通过AI智能系统对图表进行解读，只需1分钟，一键生成行业专利分析报告。
内容可寻址存储器热门专利
QQ群二维码
意见反馈
意见反馈