Test system for large scale integrated circuits
阅读：541发布：2023-12-14
专利汇可以提供Test system for large scale integrated circuits专利检索，专利查询，专利分析的服务。并且A system for testing large scale integrated circuits. The circuitry in an integrated package such as a card, module or a semiconductor chip is viewed as a partially functional logic unit. This circuitry is complemented with off-package logic to allow the combination to act as a complete functional logic unit to which functional test patterns may be applied. The complementary logic is preferably simulated in the memory of a computer-controlled tester.，下面是Test system for large scale integrated circuits专利的具体信息内容。
1. A system for testing a complex logic circuit which may be characterized as a partially functional circuit comprising: a source of a functional test pattern; a logic simulator having functional properties complementary to said partially functional circuit; means for selectively applying said test pattern to input terminals of said partially functional circuit and said logic simulator; first interface means resonsive to signals from predetermined output terminals of said partially functional circuit for applying said output signals to related input terminals of said logic simulator; second interface means responsive to signals from predetermined output terminals of said logic simulator for applying said output signals to related input terminals of said partially functional circuit; said partially functional circuit and said logic simulator being interconnected by said first and second interface means to form a fully functional circuit; and means responsive to output signals from the output terminals of both said partially functional circuit and said logic simulator for generating indications of the output signal pattern generated by said partially functional circuit and said logic simulator in response to said functional test pattern.
2. A system as in claim 1 wherein said source of functional test patterns also generates an output signal pattern expected to be generated from said partially functional circuit and said logic simulator output terminals and further comprising: means for comparing said expected pattern with said actual pattern.
3. A system as in claim 2 and further comprising: error detection means responsive to said comparing means for indicating an error when said expected pattern is different from said actual pattern.
4. A system as in claim 1 wherein said first interface means comprises: means for connecting each output terminal of said partially functional circuit to the input terminals of said logic simulator; and programmable switch means for connecting only said predetermined output terminals of said logic simulator.
5. A system as in claim 4 wherein: the output signals from said partially functional circuit are voltage levels; and said first interface means includes first level conversion means for converting said voltage level signals to binary signals to which said simulated logic circuit is responsive.
6. A system as in claim 1 wherein said second interface means comprises: means for connecting each output terminal of said logic simulator to the inputs terminals of said partially functional circuit; and programmable switch means for connecting only said predetermined output terminals of said logic simulator to said related input terminals of said partially functional circuit.
7. A system as in claim 6 wherein: the output signals from said logic simulator are binary signals; and said second interface means includes second level conversion means for converting said binary signals to voltage level signals to which said partially functional circuit is responsive.
8. A system as in claim 1 wherein said source of functional test pattern generates binary test signals, said logic simulator is responsive to binary signals, said partially functional circuit is responsive to voltage level signals, and further comprising: first digital-to-analog conversion means for converting binary signals from said applying means into voltage level signals to which said partially functional circuit is responsive.
9. A system as in claim 8 wherein said source of a functional test pattern also generates a binary output signal pattern expecTed to be generated from said partially functional circuit and said logic simulator output terminals and further comprising: second digital-to-analog conversion means for converting that portion of said output pattern expected to be generated from said partially functional circuit into voltage level signals; analog comparison means for comparing said voltage level signals of said expected pattern with the actual output pattern generated by said partially functional circuit; and binary comparison means for comparing that portion of said output pattern expected to be generated from said logic simulator with the actual output pattern generated by said logic simulator.
10. A system as in claim 9 and further comprising: analog error detection means responsive to output signals from said analog comparison means for indicating an error when said expected pattern of voltage level signals is different from said actual pattern of voltage level signals; and binary error detection means responsive to output signals from said binary comparison means for indicating an error when said expected pattern of binary signals is different from said actual pattern of binary signals.
11. A system for testing a complex logic circuit which may be characterized at a partially functional circuit comprising: a source of a functional test pattern; a logic simulator having functional properties complementary to said partially functional circuit; means for selectively applying said test pattern to input terminals of said partially functional circuit and said logic simulator; first programmable switch means for connecting predetermined output terminals of said partially functional circuit to related input terminals of said logic simulator; second programmable switch means for connected predetermined output terminals of said logic simulator to related input terminals of said partially functional circuit; and means responsive to output signals from the output terminals of both said partially functional circuit and said logic simulator for generating indications of the output signal pattern generated by said partially functional circuit and said logic simulator in response to said functional test pattern.
12. A system as in claim 11 wherein said source of functional test patterns also generates an output signal pattern expected to be generated from said partially functional circuit and said logic simulator output terminals and further comprising: means for comparing said expected pattern with said actual pattern.
13. A system as in claim 12 and further comprising: error detection means responsive to said comparing means for indicating an error when said expected pattern is different from said actual pattern.
14. A method for testing a complex logic circuit which may be characterized as a partially functional circuit comprising: providing a logic simulator having functional properties complementary to said partially functional circuit; interconnecting predetermined output terminals of said partially functional circuit to related input terminals of said logic simulator; interconnecting predetermined output terminals of said logic simulator to related input terminals of said partially functional circuit whereby said interconnected partially functional circuit and logic simulator form a fully functional circuit having functional input and output terminals; applying a functional test pattern selectively to said functional input terminals; said test pattern being designed to exercise said fully functional circuit to cause it to perform the desired function; reading output signals from said functional output terminals to determine the response of said circuit to said input functional test pattern; and comparing said response to an expected output functional test pattern to determine whether there is a difference between the expected pattern and the actual pattern.
15. A method as in claiM 14 wherein said complex logic circuit is one of a production lot of circuits having the same logic and electrical properties and further comprising the steps of: reading signals from said predetermined output terminals of said logic simulator, the combination of said input functional test pattern and said simulator signals comprising an input non-functional test pattern; and reading signals from said functional output terminals as well as from said predetermined output terminals of said partially functional circuit, the combination of said signals comprising an output non-functional test pattern.
16. A method as in claim 15 wherein the remainder of said production lot of partially functional circuits are tested by the steps of: applying said input non-functional test pattern to, and reading output response signals from, the partially functional circuit under test; and comparing said response to an expected output non-functional test pattern to determine whether there is a difference between said output response signals and said expected pattern.
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