| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | System and method for block diagram simulation context restoration | US10639044 | 2003-08-11 | US07801715B2 | 2010-09-21 | John Edward Ciolfi; Pieter J. Mosterman |
| A method of saving portions of a simulation or execution engine image at various points in a simulation or execution is disclosed. The saving of the simulation or execution context in addition to the more traditional saving of the system state information enables the restoration of a simulation or execution that is capable of producing, in a subsequent simulation or execution of a block diagram continuing from the point of the saved simulation or execution, results that are identical to those of the initial simulation or execution. The ability to restore more than just system state variables enables a user to run multiple variations of a simulation from a given point without having to replicate the simulation up until the point of the saved initial simulation, and the ability to run multiple iterations of a block diagram execution in a non-simulation execution from a given point without having to replicate the execution of the block diagram up until that point. | ||||||
| 162 | PROGRAM GENERATING APPARATUS AND BLOCK DIAGRAM GENERATING APPARATUS | US12361704 | 2009-01-29 | US20090199157A1 | 2009-08-06 | Ena Ishii; Mitsunobu Yoshida |
| The apparatus of the present invention includes a block diagram dividing unit that divides a block diagram into a plurality of pieces at a branch point, connects a branch point block element to one end of a data line which has been connected to the branch point at each divided piece and thereby generates a plurality of block diagram pieces, a program instruction generator that generates program instructions for performing processing on each block diagram piece, an execution sequence determining unit that determines an execution sequence of generated program instructions, a structural information generator that generates structural information of each of the block diagram pieces and a program generator that arranges the program instructions according to the execution sequence, writes structural information of each block diagram piece into a comment line of each of the program instructions corresponding to each of the block diagram pieces and thereby generates a program. | ||||||
| 163 | MODE-SWITCHED VARIABLE SIGNAL ATTRIBUTES IN BLOCK DIAGRAMS | US12252536 | 2008-10-16 | US20090132993A1 | 2009-05-21 | Ramamurthy Mani; Dong Jia; Haihua Feng; Alongkrit Chutinan; Qu Zhang; Vijay Raghavan |
| A programming element is provided that defines model attributes in response to mode change events in a graphical modeling environment. Such definition may involve any signal attribute such as dimensions, data types, complexity and sample times. Events that trigger definition of model attributes may be explicit signaling events generated by other elements, elements within the block diagram programming environment, and elements external from the environment. Implicit events may also trigger definition of model attributes, such as a change of attribute in an input signal. | ||||||
| 164 | Active Block Diagram For Controlling Elements In An Electronic Device | US11562397 | 2006-11-21 | US20080059837A1 | 2008-03-06 | James M. Dematteis; Phillipe A. Melman; Alan N. Wight; Timothy Griesser; Thomas M. Wright |
| A method and apparatus for controlling elements in an electronic device is via a graphical block diagram of the electronic device which displays the elements. The block diagram is coupled to the electronic device so that an operator controls the elements via the block diagram. In one embodiment of the invention, the operator uses the block diagram for selecting a combination of components and latches in the electronic device for establishing prescribed signal paths connecting the combination. | ||||||
| 165 | System and method for block diagram simulation context restoration | US11894681 | 2007-08-21 | US20080059739A1 | 2008-03-06 | John Ciolfi; Pieter Mosterman |
| A method of saving portions of a simulation or execution engine image at various points in a simulation or execution is disclosed. The saving of the simulation or execution context in addition to the more traditional saving of the system state information enables the restoration of a simulation or execution that is capable of producing, in a subsequent simulation or execution of a block diagram continuing from the point of the saved simulation or execution, results that are identical to those of the initial simulation or execution. The ability to restore more than just system state variables enables a user to run multiple variations of a simulation from a given point without having to replicate the simulation up until the point of the saved initial simulation, and the ability to run multiple iterations of a block diagram execution in a non-simulation execution from a given point without having to replicate the execution of the block diagram up until that point. | ||||||
| 166 | Translating of geometric models into block diagram models | US10744513 | 2003-12-22 | US07292964B1 | 2007-11-06 | Arnav Mukherjee; Victor Chudnovsky; Jeff Wendlandt; Nathan Brewton |
| Methods and systems for translating models generated in one modeling environment into models that can be used in other modeling environments are disclosed. Models are created using different data formats in different modeling environments. These data formats are generally incompatible with each other. Therefore, the present invention provides a neutral data format that can store information relating to models generated in one modeling environment, and that can be used by other modeling environments to create their models. The present invention may export models created in one modeling environment into the neutral data format. The neutral data format may subsequently be imported into other modeling environments in which new models are generated using the information contained in the neutral data format. The present invention also provides animation of the newly generated models by animation clients via open animation interfaces that support multiple animation clients at a simultaneous time. | ||||||
| 167 | Implicit frame-based processing for block-diagram simulation | US09908096 | 2001-07-18 | US07275026B2 | 2007-09-25 | Ramamurthy Mani; Don Orofino |
| A run-time, frame-based processing mechanism executes a block diagram model by propagating frame attributes information from blocks on which a user specified the frame attributes information to all other blocks in the block diagram model. The frame attributes information includes an indicator that specifies whether or not the data flowing from one block to another is sample-based or frame-based, as well as the size of the frame in terms of number of samples and number of channels. | ||||||
| 168 | System and method for optimizing block diagram models | US11437903 | 2006-05-19 | US20060212284A1 | 2006-09-21 | Donald Orofino; Michael Longfritz; Ramamurthy Mani; Darel Linebarger |
| A method includes in a system determining a constraint for constraining operation of a portion of a block diagram model, determining if the portion of the block diagram model violates the constraint, and providing a user information based on the violating of the first constraint. | ||||||
| 169 | System and method for block diagram simulation context restoration | US10639044 | 2003-08-11 | US20050216248A1 | 2005-09-29 | John Ciolfi; Pieter Mosterman |
| A method of saving portions of a simulation or execution engine image at various points in a simulation or execution is disclosed. The saving of the simulation or execution context in addition to the more traditional saving of the system state information enables the restoration of a simulation or execution that is capable of producing, in a subsequent simulation or execution of a block diagram continuing from the point of the saved simulation or execution, results that are identical to those of the initial simulation or execution. The ability to restore more than just system state variables enables a user to run multiple variations of a simulation from a given point without having to replicate the simulation up until the point of the saved initial simulation, and the ability to run multiple iterations of a block diagram execution in a non-simulation execution from a given point without having to replicate the execution of the block diagram up until that point. | ||||||
| 170 | Portable electronic equipment having function of drawing box chart | US994313 | 1992-12-21 | US5734382A | 1998-03-31 | Michiaki Kuno |
| A portable electronic device has a function of drawing a box chart for statistical display. The device comprises a keyboard for inputting data, a statistical processor (for determining statistic values by performing a statistical analysis of the statistical data and for producing a box chart from the determined statistic values to visually show a plurality of statistics values as label together), and a display device for displaying the produced box chart with the statistical values, thereby displaying a means value, a maximum value, a minimum value and a standard deviation value as a box chart. | ||||||
| 171 | Block diagram simulator using a library for generation of a computer program | US514725 | 1990-04-26 | US5313615A | 1994-05-17 | William C. Newman; Paul F. Titchener; Douglas B. Powell |
| Method for ordering computer software procedures in an order using a computing machine for modeling each of multiple blocks of a block diagram. The block diagram is capable of having at least one feedback loop. Each block corresponds to a software procedure for performing at least one function and has at least one input or at least one output. The block diagram has interconnections between such inputs and outputs of such blocks forming a block diagram. A list of inputs for each of such blocks is generated; a list of outputs for each of such blocks is generated; a feed-through list for each of at least some of such outputs of such blocks is generated. Each feed-through list has a list of any input which directly affects the output of the same block. The input, output and feed-through lists are machine processed for ordering of such procedures in the order during modeling. | ||||||
| 172 | 財務諸表の構成図およびそれを出力するプログラム | JP2015099564 | 2015-05-15 | JP2016218532A | 2016-12-22 | 平田 治 |
| 【課題】財産や利益の存在を視覚的に強調することにより、企業の経営成績や財務情況などの情況を見やすくできる財務諸表の構成図およびそれを出力するプログラムを提供する。 【解決手段】財務諸表における第1の金額と第2の金額および第3の金額が出力された構成図であって、 上記第3の金額が、上記第1の金額と上記第2の金額の差額であり、 上記第1の金額を表す第1の棒グラフが、第1の基準軸から第1の方向に延びるように記され、 上記第2の金額を表す第2の棒グラフが、上記第1の基準軸から上記第1の方向に延びるように記され、 上記第3の金額を表す第3の棒グラフが、上記第1の基準軸に対抗して平行するように設けられた第2の基準軸から上記第1の方向と反対の第2の方向に延びるように記されている。 【選択図】図1 |
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| 173 | Electronic device and program including block diagram display function | JP2009113823 | 2009-05-08 | JP2010262179A | 2010-11-18 | UEJIMA HIROSHI |
| <P>PROBLEM TO BE SOLVED: To provide an electronic device including a block diagram display function of allowing effective learning by creating a block problem according to a predetermined rule based on a block diagram input optionally by a user. <P>SOLUTION: This electronic device creates a block diagram in block problem creating mode, by block diagram manual creation processing of inputting and displaying each block of the same size, and creating a block diagram desired by the user according to the predetermined block rule, or by block diagram automatic creation processing of sequentially and automatically inputting and displaying the same blocks on random surfaces of the blocks according to the predetermined block rule and creating a block diagram having a desired number of blocks. A plane drawing of the created block diagram as block diagram information 17a1, and the position of each block constituting the block diagram as block array information (including the number of blocks) 17a2 are stored in a block problem storage region 17a. In block problem exercise mode, the created block diagram is displayed, and, when the number of blocks is input by the user, it is determined whether the number is equal to the stored number of blocks and the result of correct/incorrect answer is displayed. <P>COPYRIGHT: (C)2011,JPO&INPIT | ||||||
| 174 | Automatic module block diagram generator and recording medium | JP26949697 | 1997-10-02 | JPH11110198A | 1999-04-23 | NITTA KENJI |
| PROBLEM TO BE SOLVED: To make the overlapped lines in a module block diagram in a source file easy to see by preparing and arranging a unique connector graphic expressing the call destination on a module called overlappingly and concerning an extracted module and the module block diagram prepared based on the calling relation. SOLUTION: A processor 3 performs various kinds of processing according to a program and in this case, it is composed of a source file analytic means and module block diagram preparing means 7 or the like. Then, the source file analytic means 4 analyzes a source file 1 and extracts the module and the calling relation. Then module block diagram preparing means 7 prepares and arranges the unique connector graphic expressing the calling destination at the module called overlappingly concerning the extracted module and the module block diagram prepared based on the calling relation and further, the means 7 prepares and arranged the relevant unique connector graphic expressing the calling source at that called module. COPYRIGHT: (C)1999,JPO | ||||||
| 175 | Method and device for interactively analyzing block diagram | JP31182693 | 1993-12-13 | JPH07160673A | 1995-06-23 | TANUMA MASAYA |
| PURPOSE: To provide a method and a device for analyzing a block diagram capable of directly performing time response calculation without approximating the mixed model of a differential equation and an algebraic equation. CONSTITUTION: By using an analysis device provided with an input means 11, a display means 12 and an operational means 13 in which the operation means 13 is composed of a block diagram data input part 14, a calculation order deciding part 15, a time response calculation means 16 and a calculated result output part 17, the time response calculation of the block diagram constituted of respective operational elements such as the algebraic operational elements of addition, subtraction, multiplication and division, etc., and time dependent dynamic operational elements of integration and first order delay, etc., and connection data indicating the flow of signals among the respective operational elements is performed. By using a loop element capable of setting an initial value and provided with the adjustment function of output so as to make the input of the elements and the output of the elements coincide as the unknown of the algebraic equation or simultaneous algebraic equations, generating the state transition equations of the dynamic operational elements and the loop element from block diagram data at the time of the time response calculation and simultaneously solving them, the time response analysis of a system provided with the algebraic equation is performed. COPYRIGHT: (C)1995,JPO | ||||||
| 176 | Method and device for analyzing time response of block diagram | JP23049091 | 1991-09-10 | JPH0573605A | 1993-03-26 | TANUMA MASAYA |
| PURPOSE:To provide analysis method/device by/in which the time response of a block diagram can stably be calculated even if time ticking DELTAt is enlarged in the time response analysis of the block diagram including plural dynamic elements whose response speed largely differs from that of algebra elements. CONSTITUTION:In the time response analysis method of the block diagram composed of the plural dynamic arithmetic elements whose response speed differs from that of the algebra arithmetic elements, and of connection data showing the flow of a signal between the arithmetic elements, a partial derivative value on the output signal of the whole dynamic arithmetic elements of an input signal for the dynamic arithmetic element is obtained by inversely following the signal, the state transition equations of the respective dynamic arithmetic elements are generated by using the derivative value and they are simultaneously solved. The device consists of a terminal 17 such as a graphic display and a computer 18 such as a work station. | ||||||
| 177 | Automatic program generating device with block diagram processing function | JP21671690 | 1990-08-17 | JPH0498532A | 1992-03-31 | SANO YASUKO |
| PURPOSE: To extremely improve the working efficiency for generation of a program by providing a program generating control means, a block diagram parts group, a block diagram program generating means, and a variable attribute control means. CONSTITUTION: A block diagram program generating means 4 analyzes the contents shown by the block diagram form system specifications 7 in accordance with the program generation goal received from a program generation control means 12. If the call-out information on a block diagram parts 91 is described in the specifications 7, the corresponding parts 91 is retrieved and read out of a block diagram parts group 9 based on the retrieving knowledge and then evolved. Then the evolved parts 91 is applied to the original specifications 7 and the detailed block diagram specifications are obtained. As a result, the working efficiency is extremely improved for generation of a program. COPYRIGHT: (C)1992,JPO&Japio | ||||||
| 178 | PROCEDE ET DISPOSITIFS DE CONTRE-MESURE POUR CRYPTOGRAPHIE ASYMETRIQUE A SCHEMA DE SIGNATURE | EP09718480.8 | 2009-01-23 | EP2248008A2 | 2010-11-10 | BENTEO, Bruno; FEIX, Benoît; NEROT, Sebastien |
| The invention relates to a method for countermeasures in an electronic component that uses a private-key asymmetrical cryptography algorithm, including the steps of generating (102) a first output data (s1) using a primitive, and (104) a protection parameter. The method further comprises the steps of converting (106), using said protection parameter, at least one of the elements of the set including the private key and an intermediate parameter obtained from the first output data (s1) in order to provide respectively first and second operands, and generating (108, 114) a second output data (s2) from an operation in which the first and second operands are involved. | ||||||
| 179 | A SYSTEM AND METHOD FOR USING EXECUTION CONTEXTS IN BLOCK DIAGRAM MODELING | EP04750234.9 | 2004-04-16 | EP1618471A2 | 2006-01-25 | CIOLFI, John; MANI, Ramamurthy; OROFINO, Donald, P., II; SHAKERI, Mojdeh; ULLMAN, Marc; YEDDANAPUDI, Murali |
| A method of controlling the conditional execution of elements and subsystems in a block diagram is disclosed. Data structures known as Execution Contexts are created and associated with individual block diagram elements and subsystems. The Execution Contexts allow execution of the associated element or subsystem upon satisfaction of a specified pre-condition. The Execution Contexts may be inherited by other elements and subsystems in the block diagram and propagated programmatically throughout the block diagram. The use of the Execution Contexts allows for efficient code generation and block diagram execution, as well as supporting modular design concepts. | ||||||
| 180 | AUTOMATIC GENERATION OF EVALUATION ORDER FOR A FUNCTION BLOCK DIAGRAM AND DETECTION OF ANY ASSOCIATED ERRORS | EP98966109.5 | 1998-12-29 | EP1049967A1 | 2000-11-08 | POWERS, Leslie, V. |
| The programming of programmable controllers and other sequential computing devices is facilitated by automatically generating an order for evaluating function blocks in a function diagram and by automatically detecting any errors in a function block diagram which would adversely affect the generation of a unique evaluation order, such as illegal cycles, disconnected subnetworks, and/or wired-OR connections. The nodes affected by the noted errors are graphically displayed to the user, who then may use a graphical interface to edit the network until all the noted errors have been corrected. A recursive procedure analogous to a topological sort may be used to automatically generate a unique evaluation order (11A, 11B, 17, 24, 12). The blocks upstream from each 'maximal' output (15) are visited recursively from the input of one block (24, 13) to the output of a preceding block (17, 11A) until a 'minimal' node (3) is reached. | ||||||
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