| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Digital video special effector | JP9966793 | 1993-04-26 | JPH0750810A | 1995-02-21 | ANDORIYUU IAN TOROU; HAWAADO JIYON TEIISU |
| PURPOSE: To obtain a digital video special effector, capable of generating an illumination effect with high cost efficiency and few alias distortions. CONSTITUTION: When an input video pixel is stored in memory 13, selectively addressed to the memory according to a function to decide an object surface and an output pixel to represent an original video which is mapped on the object surface is generated, intensity of the original pixel is corrected before the output pixel is written in the memory by a writing side illumination effect processor 19. The original video is divided into many tiles, and mapping of corner of the tiles to the object surface is calculated 32 and vertical lines to respective pixels are calculated. A scalar product of the vertical lines is calculated, an illumination intensity correction coefficient is generated 33 along with the other coefficients, and the illumination effect processor is controlled by the coefficient. | ||||||
| 182 | Io mapping method/system for system bus | JP5599098 | 1998-02-20 | JPH11238029A | 1999-08-31 | HIROMOTO SATORU |
| PROBLEM TO BE SOLVED: To provide the IO mapping system of a system bus that eliminates the restriction of capacity by effectively using an IO space and that enables connection of a device which requires the IO space of large capacity, and that suppresses/reduces the increase of a circuit scale. SOLUTION: The system is provided with a base address register 105 where a value for deciding an IO address space is set, a comparator 106 comparing the value of the base address register 105 with an address transmitted on a system bus 100 that responses to the system bus 100 when they are matched and that makes a selection signal active, and a decoder 104 that inputs the address on the system bus 100 and the selection signal, and that maps the device so as to avoid alias space and that generates the selection signal of the device. COPYRIGHT: (C)1999,JPO | ||||||
| 183 | SIGNALANALYSATOR UND VERFAHREN ZUM ANZEIGEN VON LEISTUNGEN VON CODEKANÄLEN | EP03759887.7 | 2003-04-29 | EP1514370A1 | 2005-03-16 | FRANKE, Jens; NITSCH, Bernhard; HELLER, Klaus |
| The invention relates to a signal analyzer and to a method for displaying capacities of code channels of a CDMA (Code Division Multiple Access) signal that contains code channels having different spreading factors. The capacity of the individual code channels is determined on the basis of a received signal. The measured capacities of the individual code channels for a specified base spreading factor are portrayed in a diagram (1), and the code channels (5, 6) having an alias capacity are indicated. A code channel, with regard to the specified base spreading factor, then has an alias capacity when the code channel having the base spreading factor (SF64, SF 128) is inactive and when a code channel (C68, C144) of a higher spreading factor (SF128, SF256), this latter code channel corresponding thereto the former code channel, is active or, in the event of orthogonal transmit diversity, the capacity of a code channel is mapped onto the code channel of the base spreading factor. | ||||||
| 184 | Load register instruction short circuiting method | US12044013 | 2008-03-07 | US07904697B2 | 2011-03-08 | Brian David Barrick; Brian William Curran; Lee Evan Eisen |
| An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken. | ||||||
| 185 | REGISTER RENAMER THAT HANDLES MULTIPLE REGISTER SIZES ALIASED TO THE SAME STORAGE LOCATIONS | US14842915 | 2015-09-02 | US20160055000A1 | 2016-02-25 | Wei-Han Lien |
| A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry. | ||||||
| 186 | Register renamer that handles multiple register sizes aliased to the same storage locations | US12938921 | 2010-11-03 | US09158541B2 | 2015-10-13 | Wei-Han Lien |
| A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry. | ||||||
| 187 | ASSIGNING EFFICIENTLY REFERENCED GLOBALLY UNIQUE IDENTIFIERS IN A MULTI-CORE ENVIRONMENT | US12649542 | 2009-12-30 | US20110161618A1 | 2011-06-30 | GREG H. BELLOWS; JASON N. DALE; BRIAN H. HORTON; JOAQUIN MADRUGA |
| A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map. | ||||||
| 188 | Load Register Instruction Short Circuiting Method | US12044013 | 2008-03-07 | US20090228692A1 | 2009-09-10 | Brian David Barrick; Brian William Curran; Lee Evan Eisen |
| An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken. | ||||||
| 189 | Scalable call management system | US09999474 | 2001-11-15 | US20030091025A1 | 2003-05-15 | Joseph Celi JR.; Brett Gavagni; Margarita Zabolotskaya |
| A scalable call management system. The system can include at least one voice server hosting one or more voice browsers, the voice server having a single communications port through which voice call requests can be processed by the voice browsers, each voice browser having a port alias through which call requests can be processed. The system also can include a call processing gateway linking telephony endpoints in a public switched telephone network (PSTN) to the voice server. Finally, the system can include a translation table mapping port aliases to respective voice browsers. | ||||||
| 190 | RETRIEVAL DEVICE, METHOD FOR CONTROLLING RETRIEVAL DEVICE, AND RECORDING MEDIUM | US14413868 | 2012-07-13 | US20150213043A1 | 2015-07-30 | Yohsuke Ishii; Shoji Kodama |
| A search device receives a search request, extracts at least one of an alias or a metadata name from the search request, converts the alias to metadata name by referring to metadata schema management information for managing in an inclusive manner a namespace alias and a metadata name for the retrieval device to identify a metadata schema definition defining the structure of a retrieval-target file that includes metadata, and specifies a field name from the metadata name by referring to schema mapping management information for managing the corresponding relationship between a metadata name of metadata schema definition information and a field name of the retrieval index schema definition. | ||||||
| 191 | Assigning efficiently referenced globally unique identifiers in a multi-core environment | US12649542 | 2009-12-30 | US08316207B2 | 2012-11-20 | Greg H. Bellows; Jason N. Dale; Brian H. Horton; Joaquin Madruga |
| A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map. | ||||||
| 192 | Register Renamer that Handles Multiple Register Sizes Aliased to the Same Storage Locations | US12938921 | 2010-11-03 | US20120110305A1 | 2012-05-03 | Wei-Han Lien |
| A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry. | ||||||
| 193 | Systems and Methods to Facilitate Commerce in the Vehicle Aftermarket | US11425140 | 2006-06-19 | US20070073595A1 | 2007-03-29 | Thomas Moore |
| A system and method for facilitating commerce, the system and method including the steps of allowing a user to select one or more items from a list presented to the user, associating the one or more items with at least one alias, mapping the one or more items into a preselected format and cataloging the mapped data so that it can be accessed by at least the user, so that the mapped data is integrated with a storefront so that the items may be located and sold using the mapped data. | ||||||
| 194 | COREFERENCE RESOLUTION IN AN AMBIGUITY-SENSITIVE NATURAL LANGUAGE PROCESSING SYSTEM | PCT/US2008074935 | 2008-08-29 | WO2009029903A2 | 2009-03-05 | VAN DEN BERG MARTIN; CROUCH RICHARD; SALVETTI FRANCO; THIONE GIOVANNI LORENZO; AHN DAVID |
| Technologies are described herein for coreference resolution in an ambiguity-sensitive natural language processing system. Techniques for integrating reference resolution functionality into a natural language processing system can processes documents to be indexed within an information search and retrieval system. Ambiguity awareness features, as well as ambiguity resolution functionality, can operate in coordination with coreference resolution. Annotation of coreference entities, as well as ambiguous interpretations, can be supported by in-line markup within text content or by external entity maps. Information expressed within documents can be formally organized in terms of facts, or relationships between entities in the text. Expansion can support applying multiple aliases, or ambiguities, to an entity being indexed so that all of the possibly references or interpretations for that entity are captured into the index. Alternative stored descriptions can support retrieval of a fact by either the original description or a coreferential description. | ||||||
| 195 | METHOD AND SYSTEM FOR TRANSFERRING DATA DIRECTLY BETWEEN STORAGE DEVICES IN A STORAGE AREA NETWORK | PCT/US2005034844 | 2005-09-27 | WO2006039347A2 | 2006-04-13 | DROPPS FRANK R; WURZER KEVIN M |
| A method and system for performing a copy operation between storage devices coupled to a Fibre Channel switch element is provided. The Fibre Channel switch element receives a user command to copy data from a source storage device to a destination storage device and controls the copying operation. The Fibre Channel switch acts as a SCSI initiator and initiates a write operation for the destination storage device and initiates a read operation for the source storage device; and uses an alias cache for intercepting messages between the destination and source storage devices. A RX_ID mapping cache is used to substitute a RX_ID so that that a Fibre Channel write target appears to the source storage device as the destination storage device, and to the destination storage device a Fibre Channel read target appears to be the source storage device. | ||||||
| 196 | METHODS AND SYSTEMS FOR UNIVERSAL PAYMENT ACCOUNT TRANSLATION | PCT/US2011/060554 | 2011-11-14 | WO2012067993A1 | 2012-05-24 | KILLIAN, Patrick, L.; MALHOTRA, Sandeep |
A method and system of transferring value from a payer participant of a first online community website to a payee participant of a second online community website through a payment account translation system is provided. The method includes initiating a first payment request, validating that the payer and payee are registered participants of the online community, translating the payer alias into a payer pseudo-account number using business rules and community participant profiles associated with the community website from which the payment request is made, and mapping the payer pseudo-account number to a respective funding/repository account primary account number (PAN). The method further includes transmitting the PANs and a validation code to a payments network for processing through the payments network and approving the transfer of value from the payer to the payee such that the PAN of the payer is unknown to the community website. |
||||||
| 197 | A MUTLI-SYSTEM SUBSCRIBER IDENTIFICATION MODULE | PCT/FI1995000409 | 1995-07-31 | WO1996004759A2 | 1996-02-15 | NOKIA TELECOMMUNICATIONS OY; HOKKANEN, Petri |
| A subscriber identification module (SIM) for storing user identities and other user-specific information and thereby enables access to the service of the radio system. One of the user identities is Temporary Mobile Subscriber Identity (TMSI) used for user anonymity purposes by utilizing it as an alias for the actual user identity in order to avoid sending the actual user identity in clear on the radio path. A part of TMSI is a random number which cannot be used to identify the user/terminal without mapping information to the actual user identity, which is found in the telecommunications network entity that allocated the random number. The present invention allows an SIM roaming from one radio system to another by utilizing predetermined bits of TMSI are used to differentiate between different TMSI's of different systems indicating in a uniform manner in all mobile radio systems the mobile radio system which has allocated the TMSI. | ||||||
| 198 | TOPOLOGY MANAGEMENT METHOD AND SYSTEM OF VIRTUAL MACHINES | US14086082 | 2013-11-21 | US20150089499A1 | 2015-03-26 | Pa HSUAN; Wen-Min HUANG; Chih-Yang LIU |
| A system for managing topology of virtual machines (VMs) includes a base-information database, an information register processing unit, and a topology information database. The base-information database records internal information of all VMs of a cloud system. The information register processing unit monitors the base-information database for updating the internal information of the VMs to the topology information database. The topology information database mainly records a mapping between an alias name and a hostname of each VM, and also records a mapping between the hostname and IP address of each VM. The alias name of each VM is defined in accordance with the task assigned to the VM in the cloud system. | ||||||
| 199 | MONEY TRANSFER SYSTEM GATEWAY SERVICE | US14535698 | 2014-11-07 | US20150066756A1 | 2015-03-05 | Patrick Killian; Sandeep Malhotra |
| Systems and methods for person-to-person and person-to-merchant remittances from a person having a closed loop system account to merchants who are not members of the closed loop system. In an embodiment, a payment gateway computer receives a remittance transaction request from a payment services provider (PSP) computer associated with a closed-loop system, maps an alias identifier into a shadow account number assigned to the sender in an open-loop payment authorization system, determines that the alias identifier mapped into a valid shadow account number, debits a stored value account for the remittance transaction amount, credits a shadow account in the open-loop payment authorization system for the remittance transaction amount, generates an authorization request for an open-loop payment transaction and transmits it to the open-loop payment authorization system, receives an authorization response from the open-loop payment authorization system, and transmits an approval response. | ||||||
| 200 | LEVERAGING CENTRALIZED MAPPING BETWEEN ORGANIZATIONS | US13341469 | 2011-12-30 | US20130173290A1 | 2013-07-04 | RYAN C. OWINGS; NNEKA AMARACHI DAWN OJI |
| Computerized systems, methods, and graphical user interfaces are provided to facilitate communication between physician offices and reference laboratories. A reference laboratory content manager provides a centralized conduit for interfacing clients placing orders for reference laboratory testing and reference laboratories performing testing. The reference laboratory content manager leverages centralized mapping across organizations by managing associations for procedures between reference laboratory aliases and client aliases. The centralized mapping enables the reference laboratory content manager to manage updates from reference laboratories and facilitate clients wishing to modify utilization of reference laboratories. | ||||||
QQ群二维码
意见反馈
意见反馈