子分类：
- H03M7/001： .{以所用的元件为特征的}
- H03M7/02： .转换到加权代码或相反转换,即对一数字的加权与该数字在信息组或代码字中的位置有关{(布斯编码器入G06F7/52C2D1,G06F7/52C2D2A)}
- H03M7/14： .转换到非加权代码或相反转换
- H03M7/26： .转换到随机码或相反转换
- H03M7/28： .可编程序结构,即代码转换器所包括的设备其算符是可变的,以调整转换程序
- H03M7/30： .压缩(用于减少冗余的语言分析-合成入G10L19/00;用于图像通信的入H04N);扩展;消除不需要的数据,例如减少冗余{(用于数据获得的入G06F17/40;用于图像数据处理的入 G06T9/00;在数据记录中减少冗余的入G11B20/14;用于传输的入H04B1/66)}
| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 261 | Apparatus, method and algorithm for encoding and decoding characters in a message to be transmitted between a first system and a second system | US838084 | 1986-03-10 | US4752765A | 1988-06-21 | Lawrence E. Larson |
| A first data processing system sends a message to a second data processing system via a modem. A processor of the first data processing system executes the instructions of an encoding algorithm stored in a memory of the first data processing system thereby encoding the characters of the message as the message is sent from the first system to the second system. The processor, in conjunction with the encoding algorithm, encodes the characters of the message by locating unacceptable characters among the acceptable characters in the message, the unacceptable characters possessing more than one meaning and triggering the execution of a function other than the intended function. The acceptable characters do not possess any alternative meanings. A bias code is selected for the acceptable characters and a further bias code is selected for the unacceptable characters. The unacceptable characters are converted into modified acceptable characters. The bias code, acceptable characters, further bias code, and modified acceptable characters are transmitted from the first data processing system to the second data processing system. The second system interprets the bias code to mean that the acceptable characters should be accepted without alteration, but interprets the further bias code to mean that the modified acceptale characters should be re-converted into the original unacceptable characters. Since the second system received the unacceptable characters in modified acceptable character form, only the intended function of the character will be executed. | ||||||
| 262 | Protocol converting apparatus for videotex system | US906257 | 1986-09-11 | US4739402A | 1988-04-19 | Satoru Maeda; Akihiko Tao |
| A protocol converting apparatus in which when character information electronic signals of a NAPLPS (North American Presentation Level Protocol Syntax) system are displayed on a user terminal apparatus of a CAPTAIN (Character And Pattern Telephone Access Information electronic signal Network) system, the overflow condition in a row direction and the overflow condition in a column direction are detected and in which in the case of the overflow condition in a column, an overflow character information electronic signal is temporarily stored in a memory, whereby the NAPLPS character information electronic signal can be used by all user terminals of the CAPTAIN system. | ||||||
| 263 | Shift circuit which need no transformation between nine-bit-byte and eight-bit-byte data | US391256 | 1982-06-23 | US4473894A | 1984-09-25 | Toshio Yagihashi |
| For use in a packed nine-bit-byte data processing system, a shift circuit comprises a shifter for subjecting a datum given by a bit sequence of nine-bit bytes to a shift of a preselected whole number N of digits or, more particularly, a shift of [9N/2] and [9(N-1)/2+5] bits when the whole number is an even and an odd integer, respectively. Before written in a register, the shifted bit sequence is edited by an editor into an edited bit sequence wherein each prescribed binary bit in each nine-bit byte is produced as it stands when the whole number is even and is placed, when the whole number is odd, at a next more significant bit than a four-bit byte which is next more significant in the shifted sequence than that binary bit. | ||||||
| 264 | Apparatus for translation of character codes for application to a data processing system | US98456 | 1979-11-29 | US4425626A | 1984-01-10 | Arthur A. Parmet; Charles W. Dawson |
| A reader/sorter reads documents which include MICR, OMR and OCR encoded characters. The reader/sorter reads each type of character sequentially at separate read head positions. Character codes read by a particular head address a separate area of address locations in a random access memory which stores equivalent character codes which are used by the data processing system. The random access memory is loaded with the translated character codes, allowing a data processing system to communicate with the reader/sorter. | ||||||
| 265 | Decoder for identification of bacteria | US831432 | 1977-09-08 | US4158199A | 1979-06-12 | John W. Clark |
| A device for the automatic conversion of binary to octal information for the identification of bacteria including switching means controlled as a function of predetermined biochemical reactions and means to convert the binary information provided by control of the position of the switches to octal information used in conjunction with an appropriate guide for identification of bacteria. | ||||||
| 266 | Electronic data processing equipment | US764558 | 1977-02-01 | US4134536A | 1979-01-16 | Seiji Saito; Ichiro Sado; Reiji Hirano |
| Disclosed is an electronic data processing equipment for specifying and identifying the radices or units of numeric data entered and converting them into numbers in predetermined radices or units so that arithmetic operations are carried out between the numbers expressed in different radices or units. Furthermore means is provided for permitting the subtraction of a number in one radix or unit from a number in another radix or unit without the use of the functional keys. | ||||||
| 267 | Circuit arrangement for monitoring the function of a dynamic decoder circuit | US745242 | 1976-11-26 | US4087044A | 1978-05-02 | Ruediger Hofmann |
| A circuit arrangement for monitoring the function of a dynamic decoder circuit which comprises at least parallel-connected decoder transistors, a pre-charging transistor, and an end stage which samples the output signal of the decoder transistors, is disclosed in which for simulating the decoder circuit, two discharge transistors are connected in parallel and have control inputs which are supplied with address signals in inverted form and in non-inverted form and whose node, which is formed by the one connection point, is precharged in that it is connected to a further transistor. In order to simulate the capacitance existing at the corresponding connection point of the parallel-connected decoder transistors of a decoder circuit, a varactor is connected to the node and the node is also connected to the further circuit elements provided in the decoder circuit between the decoder transistors and the end stage. For simulating the capacity load formed by the end stage of the decoder circuit, a further varactor is provided which is subsequently connected to the further circuit elements. | ||||||
| 268 | Electronic calculator for feet-inch-fraction numerics | US692757 | 1976-06-04 | US4081859A | 1978-03-28 | Alan B. Goldsamt; Earl Greenberg |
| An apparatus is disclosed for automatically adding, subtracting, multiplying and dividing feet, inches and fractions of an inch and for the recordation of the results of said arithmetic functions on a visual display. The apparatus also automatically and directly converts feet, inches and fractions of an inch into decimal equivalents and into the metric system of measurement and, similarly, converts numbers in decimal numeric and in metric measurement automatically and directly into feet, inches and fractions of an inch. | ||||||
| 269 | Storage device with row flag elements for row scanning | US50978274 | 1974-09-27 | US3927396A | 1975-12-16 | LE CAN CLAUDE JAN PRINCIPE FRE |
| A storage device, including a matrix of storage elements arranged in rows and columns, a flag element in each of the rows, a scanning register for scanning the rows to detect the presence of a flag in one of the rows, and a data transfer device for transferring a portion of the information stored in a row in which a flag has been detected.
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| 270 | Decode circuit | US40768173 | 1973-10-18 | US3911428A | 1975-10-07 | CHIN WILLIAM BENEDICT |
| A decode circuit for use in a decoder employing switches such as complementary metal oxide semiconductor (CMOS) field effect transistors, utilizing cascaded (series-connected) switches of one channel type and a pair of cascoded (parallel-connected) switches of the opposite channel type. In the quiescent state the output lines of the decode circuits are clamped to ground to assure that substantially no power is dissipated. When the decoder system is in the select state, the output lines of the unselected decode circuits remain clamped to ground. The circuit has the advantage that it requires only a pair of cascoded switches plus a strobe switch connected in series with the data switches for operation. This results in a considerable savings of the devices required over prior art decode circuits of this type.
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| 271 | Minimum pitch mosfet decoder circuit configuration | US53574874 | 1974-12-23 | US3909808A | 1975-09-30 | COCHRAN WILLIAM HUGH; HEUER DALE ARTHUR; SHEEHAN MICHAEL JAMES |
| MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby, increasing the number of decoded lines of the conventional decoder. In addition, the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. For particular physical layout ground rules utilized in fabrication of an integrated decoder of the instant invention, the binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density.
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| 272 | Dynamic data input latch and decoder | US44150074 | 1974-02-11 | US3902082A | 1975-08-26 | PROEBSTING ROBERT JAMES; GREEN ROBERT SHERMAN |
| A dynamic input latch and address decoder for use in the large scale MISFET integrated circuits such as dynamic random excess memories or the like is disclosed. The circuit includes an input latch which responds to a single low voltage logic input to produce and hold high voltage true and complement logic signals during a dynamic cycle. Both true and complement signals are at logic 0 level during a precharge period. Some number, N, of input latches are combined with 2N decoder/line drivers which utilize the logic zero levels of both the true and complement outputs of the latches during the precharge cycle to produce a dynamic decoder which consumes substantially no power. The circuit also utilizes bootstrap capacitors to produce the highest levels and fastest transitions possible for the circuit.
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| 273 | Address selection circuit for storage arrays | US43815974 | 1974-01-31 | US3866176A | 1975-02-11 | BAITINGER UTZ G; HAUG WERNER OTTO; ILLI MANFRED |
| For each binary position of the coded addresses the selection device shows a phase splitter whose two outputs are connected to associated inputs of decoders. In order to increase the noise resistance jointly clocked AND gates are inserted at the inputs and outputs of the phase splitters, and at the outputs of the decoders. An automatic optimum determination of the conditioning time of the AND gates at the outputs of phase splitters is achieved by a delayed clock pulse DCS1 derived from a clock pulse T of AND gates at the input of the phase splitters. For that purpose, clock pulse T is derived at the output of the AND gates at the input of phase splitters and, via a simulated phase splitter circuit integrated on the chip, is applied as clock pulse DCS1 to the clock inputs of the AND gates at the output of the functional phase splitters. The determination of the conditioning time of AND gates at the output of the decoder is performed accordingly at the output of decoder. In that process, a clock signal is derived from the output of AND gates at the output of phase splitters, and applied as a delayed clock signal DCS2 via a simulation of one of decoders to the clock inputs of the AND gates at the output of the decoders.
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| 274 | Monolithic decoder circuit | US3795828D | 1973-03-08 | US3795828A | 1974-03-05 | CAVALIERE J; MOONEY D |
| A monolithic decoder circuit provides a decode function with driving capabilities at opposite ports and requires only a single layer of metallization. The circuit comprises a plurality of gates each including a pair of transistors formed by emitter diffusions in a base area. Current switches are connected to the emitters of the transistors to provide inputs and emitter followers are connected to the bases of the transistors to provide outputs.
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| 275 | Light-emitting diode display | US3771015D | 1972-02-09 | US3771015A | 1973-11-06 | MILLER C |
| A visual display adapted to show an analog presentation which represents the value of a measured parameter, in response to coded digital electrical input signals that are proportional to the parameter. In one embodiment a column of energizable light elements is provided, along with logic circuit means for selecting and energizing a series of groups of elements of the column to form a visual display which represents a numerical value between 0 and 50. In another embodiment the logic circuit is utilized to control, sequentially, three light columns, each having a different scale value.
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| 276 | Method of controlling high electric field domain in bulk semiconductor | US3766372D | 1971-05-14 | US3766372A | 1973-10-16 | KATAOKA S; HASHIZUME N; KOMAMIYA Y; MORISUE M; TATENO H; KAWASHIMA M |
| The invention disclosed is for a method and apparatus for controlling high electric field domain in a bulk semiconductor as well as an information processing method thereby. By means of a capacitive electrode, the high electric field domain may be either sustained or extinguished.
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| 277 | Device for interchanging measurement systems | US3764781D | 1972-07-10 | US3764781A | 1973-10-09 | KREITHEN M; LAWLER J |
| The output from a control means providing pulses representative of English system units is applied to a countermeans, which, as it counts the input pulses applies the count as an output to a memory means. The memory means contains storage locations corresponding to permissible counts of counter to provide a pattern of predetermined fixed relationship between the English and Metric system, such that for each input count a predetermined output in terms of Metric measurement is provided. The memory system also provides means for adjusting the count in the counter and specifically, depending upon the direction of counting, readjusts the counter to zero upon completion of a predetermined number of steps in a repeatable pattern and when counting down skips the counter to the last predetermined count of a finite number of steps in said pattern.
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| 278 | High speed serial scan and read-out of keyboards | US3745536D | 1971-03-01 | US3745536A | 1973-07-10 | KLEHM W |
| Relates generally to the production of electrical signals from a keyboard, each key of which is individually operatively associated with a switching device whose activation to electrical conductive condition is controlled by the displacement of the key. These switches are hermetically sealed from the atmosphere and are electrically scanned in succession at relatively high speeds and at a repetitious rate such that several scanning cycles occur during the normal activation of a selected key. The keyboard mechanism also includes a shift register having one more bit position than the number of switch devices and into which a bit is introduced into the ''''one'''' position at the instant the scan encounters a closed switch of the keyboard. This bit is then shifted through the register in timed relation to the scan of the remaining key switches and unloaded into the last bit position of the register. A detector senses the presence of a bit in both the ''''one'''' position and the last position of the shift register and upon detection of a bit solely in the one position it delivers a signal indicative of the character represented by the actuated key and upon detecting bits in the two extreme positions of the shift register it nullifies the delivery of such a signal.
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| 279 | System for monitoring the decoding of an address | US15683471 | 1971-06-25 | US3719816A | 1973-03-06 | COFFRE P; DARMON J |
| A system for checking the decoding of an address previously encoded in the form of a group of N bits called input bits. The system performs, on one hand, a re-encoding of such address in the form of N output bits identical to the N input bits, and in the form of their complementary bits N, and, on the other hand, compares the identity and/or complementarity of the input and output bits. The system comprises a first arrangement of 2N relays each having a single contact, a group of n diodes (D1, D2, etc.) per contact, a group of n re-encoding matrices (M1, M2 etc.), a second arrangement of 2N relays each having a contact, and means for comparing the identity and/or the complementarity of the input and output bits.
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| 280 | Logic for color bar printer | US3713138D | 1970-06-30 | US3713138A | 1973-01-23 | GIRARD D |
| A printer, which includes a pair of green printing elements and a pair of black printing elements, causes a sequence of green, black, and white colored bars to exist on a tag, where the green and black bars are printed and the white bars are the tag color resulting from a lack of printing. The tag is moved through the printer in discrete steps of two bar widths at a time, so that two new areas of the tag are beneath each pair of printing elements after each discrete movement. Signals are then applied to those printing elements which are to then print bars. A ribbon, which is associated with each pair of printing elements, is moved one bar width each time a print signal is applied to the pair of printing elements. This movement occurs after the leading one of the printing elements prints and before the trailing one of the printing elements prints. Logic circuitry is also included for converting a binary code into signals representing the colored bar code and for providing necessary signals to the printing elements and ribbons. The code-converting circuitry uses a module three up-down counter, and the then-existing count in the counter represents the then-required color bar.
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