| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 221 | DIGITAL-ANALOG CONVERSION METHOD AND DEVICE | EP15803068.4 | 2015-06-02 | EP3151431A1 | 2017-04-05 | LEE, Jongwoo; CHO, Thomas Byunghak |
The present invention relates to a digital-analog conversion method and device for adjusting a reference current to be used in a digital-analog conversion, by using a common mode feedback device, and the digital-analog conversion method of the present invention comprises the steps of: generating a reference current by receiving a reference voltage; converting a digital signal into an analog signal by receiving the generated reference current; detecting a common mode voltage, which is the average value of a both-end voltage of the converted analog signal; comparing the detected common mode voltage with the reference voltage; generating a feedback signal on the basis of the comparison result; and adjusting the reference current according to the generated feedback signal. |
||||||
| 222 | TRANSMITTER DIGITAL-TO-ANALOG CONVERTER (DAC)- BASEBAND FILTER (BBF) COMMON MODE INTERFACE | EP15727227.9 | 2015-05-22 | EP3149849A1 | 2017-04-05 | CHEN, Minghui; RANJAN, Mahim; GOLDBLATT, Jeremy Mark; BOSSU, Frederic |
| Removing common-mode current from a pair of complementary current signals, including: generating a common-mode voltage of the pair of complementary current signals including at least a first current signal and a second current signal; measuring and outputting a difference voltage between the generated common-mode voltage and a common-mode reference voltage; and removing at least a portion of the common-mode current from the first current signal and the second current signal based on the difference voltage. | ||||||
| 223 | MUSIC REPRODUCING DEVICE | EP16182386.9 | 2016-08-02 | EP3139499A1 | 2017-03-08 | ASAO, Kei; KAWAGUCHI, Tsuyoshi; YOSHIDA, Makoto; SHIOZAKI, Takanori; NAKANISHI, Yoshinori; ASAHARA, Hiroyuki; KITAGAWA, Norimasa |
Problem: To realize active control ground that sets inverted output of an amplification circuit to ground with simple configuration. Solution: A DAP 1 comprises a positive side DAC 7 that D/A-converts digital audio data into analog audio data, a positive side amplification circuit 9 that amplifies the analog audio data that the DAC 7 D/A-converts, a negative side DAC 8 that D/A-converts the digital audio data into the analog audio data, and a negative side amplification circuit 10 that amplifies the analog audio data that the DAC 8 D/A-converts, and a CPU 2. The CPU 2 mutes the DAC 8 in case of an ACG mode that sets output of the amplification circuit 10 to ground.
|
||||||
| 224 | VERFAHREN ZUR ERZEUGUNG EINER HOCHFREQUENZLEISTUNG UND LEISTUNGSVERSORGUNGSSYSTEM MIT EINEM LEISTUNGSWANDLER ZUR VERSORGUNG EINER LAST MIT LEISTUNG | EP13830207.0 | 2013-12-18 | EP2936541B1 | 2017-02-01 | GREDE, André; KRAUSSE, Daniel; LABANC, Anton; THOME, Christian; PENA VIDAL, Alberto |
| 225 | VOLTAGE DOUBLING CIRCUIT FOR AN ANALOG TO DIGITAL CONVERTER (ADC) | EP15706980.8 | 2015-02-09 | EP3111558A1 | 2017-01-04 | ALLADI, Dinesh Jagannath; BAKER, Sean; SIVAKUMAR, Balasubramanian; HUANG, Wei; YUAN, Dan |
| In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors. | ||||||
| 226 | METHOD AND APPARATUS FOR TRANSMITTING VIDEO SIGNAL | EP14888240.0 | 2014-11-04 | EP3107283A1 | 2016-12-21 | KIM, Do Kyun; SONG, Jin Gun; KIM, Dong Han |
Provided are a method and an apparatus for transmitting a video signal, the method converting a digital video signal into an analog video signal. The method and apparatus for transmitting a video signal determine the specification of an analog video signal transmission, convert the digital timing of a digital video signal on the basis of the determined specification, convert the converted digital video signal into an analog video signal, and transmit the converted analog video signal. |
||||||
| 227 | LOW-RIPPLE LATCH CIRCUIT FOR REDUCING SHORT-CIRCUIT CURRENT EFFECT | EP16159599.6 | 2016-03-10 | EP3093993A2 | 2016-11-16 | HO, Chen-Yen; LIN, Yu-Hsin |
A latch circuit (300) includes an input stage (310), an amplifying stage (MN1, MN2, MP1, MP2) and a clock gating circuit (320). The input stage (310) is arranged for receiving at least a clock signal and a data control signal. The amplifying stage (MN1, MN2, MP1, MP2) is coupled to the input stage (310) and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit (320) is coupled to the amplifying stage (MN1, MN2, MP1, MP2), and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.
|
||||||
| 228 | METHODS, DEVICES, AND SYSTEMS FOR SWITCHED CAPACITOR ARRAY CONTROL TO PROVIDE MONOTONIC CAPACITOR CHANGE DURING TUNING | EP13816182 | 2013-06-12 | EP2872997A4 | 2016-06-29 | MORRIS ARTHUR S III |
| 229 | PULSE DENSITY DIGITAL-TO-ANALOG CONVERTER WITH SLOPE COMPENSATION FUNCTION | EP14725255.5 | 2014-03-11 | EP2973973A2 | 2016-01-20 | KRIS, Bryan; REITER, Andreas; FUTO, Tibor; DUMAIS, Alex |
| A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. This slope compensation function may be provided by a digital slope compensation generator and a pulse density modulated digital-to-analog converter (PDM DAC) having a selectable response mode low pass filter. | ||||||
| 230 | SINGLE-CHIP MULTI-DOMAIN GALVANIC ISOLATION DEVICE AND METHOD | EP13778241 | 2013-04-17 | EP2839583A4 | 2016-01-20 | MOGHE YASHODHAN VIJAY; TERRY ANDREW |
| 231 | ENHANCED SECOND ORDER NOISE SHAPED SEGMENTATION AND DYNAMIC ELEMENT MATCHING TECHNIQUE | EP13859273.8 | 2013-11-20 | EP2926459A1 | 2015-10-07 | NGUYEN, Khiem, Quang; ADAMS, Robert |
| A method and circuit to perform noise shaped splitting of a digital input signal may include using multiple layers to process the input signal. In the first layer, the most significant bits of the input signal may be distributed to a plurality of branches. Dynamic element matching may be performed using the least significant bits of the input signal. Based on the results of the dynamic element matching, values may be added to the plurality of branches. If there is insufficient data activity, dynamics enhancement may be performed to increase the data activity. The output signals of each of the plurality of branches in the first layer may be provided to a second layer, in which these steps can be repeated on each of the output signals. The outputs of the second layer may be provided to a plurality of three level unit elements. | ||||||
| 232 | APPARATUS AND METHOD FOR CONVERTING ANALOG SIGNAL TO DIGITAL SIGNAL | EP12857083 | 2012-12-13 | EP2792076A4 | 2015-08-19 | LEE JONG-WOO |
| An apparatus of a Digital-to-Analog Converter (DAC) is provided. The apparatus includes a logic circuit for performing a logical operation based on a combination of bit values b0 through bN-1 of a digital code, and a plurality of switches for controlling an output state of a plurality of current cells based on an output of the logical operation, wherein the plurality of the current cells respectively output currents under a control of respective ones of the plurality of switches. | ||||||
| 233 | SINGLE-CHIP MULTI-DOMAIN GALVANIC ISOLATION DEVICE AND METHOD | EP13778241.3 | 2013-04-17 | EP2839583A1 | 2015-02-25 | MOGHE, Yashodhan, Vijay; TERRY, Andrew |
| An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween. | ||||||
| 234 | Clock signal error correction in a digital-to-analog converter | EP14159962.1 | 2014-03-14 | EP2779462A1 | 2014-09-17 | Schafferer, Bernd; Lai, Ping Wing; He, Quirong |
In an example, there is disclosed herein a digital-to-analog converter (DAC) including a correction circuit for a clock, including a differential clock. Error correction may take place within the DAC core, by means of replica cells that are substantially similar to conversion cells. Rather than contributing their output to the converted signal, the replica cells may be configured to provide a feedback signal to a clock receiver with information for correcting the clock signal. The feedback signal may be operable to correct errors, for example, in duty cycle and crosspoint, as measured at the DAC core.
|
||||||
| 235 | SAMPLING CIRCUIT, A/D CONVERTER, D/A CONVERTER, CODEC | EP12842682.2 | 2012-12-27 | EP2642666A1 | 2013-09-25 | NAKANISHI, Junya; NAKANISHI, Yutaka; NAKAMOTO, Seiko |
An A/D converter comprising: a sampling circuit (140) including a continuous section (130a), a sampling and holding section (130b) for intermittently sampling an input signal based on an analog signal input from the continuous section (130a) to hold and transfer the sampled signal, and a digital section (130c) for outputting a signal transferred from the sampling and holding section (130b) as a digital signal; and a control circuit (139) for supplying a clock signal (φ1) in which jitter is not added to the continuous section (130a) and supplying a clock signal (φ2') in which the jitter is added to the sampling and holding section (130b). |
||||||
| 236 | D/A CONVERSION DEVICE, PERIPHERAL DEVICE, AND PLC | EP10857774.3 | 2010-09-28 | EP2624459A1 | 2013-08-07 | ONISHI, Atsuko; KUBOTA, Yoshiyuki |
A D/A converter according to the present invention includes a wave-form data-array memory means for memorizing a wave-form data array configured of a plurality of digital values, a wave-form output-format data memory means for memorizing wave-form output-format data designating a wave-form output period, a digital value output means for sequentially reading out the digital values for each wave-form output period from the wave-form data-array memory means and outputting the values, and a D/A conversion means for converting the digital values outputted from the digital value output means into analog-data values. |
||||||
| 237 | Procédé et dispositif de configuration de circuits électriques et/ou électroniques | EP11187230.5 | 2011-10-31 | EP2451082B1 | 2013-06-05 | Morche, Dominique |
| 238 | METHOD AND APPARATUS FOR BANDPASS DIGITAL TO ANALOG CONVERTER | EP10821041.0 | 2010-09-20 | EP2484015A1 | 2012-08-08 | PETROVIC, Branislav |
| Systems and methods for providing a mechanism by which digital signals can be converted to analog signals with an efficient structure that reduces the number of filters required by providing a mechanism for cancelling images that would otherwise be generated. By adjusting three parameters in the system, a selection can be made as to whether to generate upper sidebands, lower sidebands and in which direction the envelope of the output from the system will be skewed. | ||||||
| 239 | CONVERTER, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM | EP08778239 | 2008-07-17 | EP2169832A4 | 2012-07-25 | HIRONAKA SATOSHI; KOHDA TOHRU; AIHARA KAZUYUKI |
| 240 | VERFAHREN ZUR VERARBEITUNG EINES ANALOG BESTIMMTEN MESSWERTSIGNALS, RESOLVERANORDNUNG ZUR DURCHFÜHRUNG DES VERFAHRENS UND VERFAHREN ZUR BESTIMMUNG EINES AUSGANGSSTROMES EINES UMRICHTERS | EP10745165.0 | 2010-08-12 | EP2471178A1 | 2012-07-04 | HAMMEL, Wolfgang; NEUMAYER, Ulrich |
| The invention relates to a method for processing an analog measurement value signal and to a resolver assembly for carrying out the method, wherein the measurement value signal is supplied to a delta-sigma modulator, which on the output side provides a bit stream, particularly a one-bit data stream, particularly having a moving average corresponding to that of the measurement value signal, wherein the bit stream is supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is, a multi-bit data stream. The first digital filter has three differentiators arranged in series, wherein the bit stream is clocked with a clock frequency f s, that is, with a clock period T s = 1/ f s, and consequently the stream of digital intermediate words is clocked with a clock frequency f D, that is, a clock period T D = 1/ f D, and is thus updated. The output signal of the first digital filter is supplied to a second digital filter, wherein the second digital filter, being the originating data word stream, has the difference between a first and a second result data word stream, wherein the first and second result data word stream are determined around a first and a second time interval from the intermediate data word stream. The first and the second time intervals are arranged with time lag T1, wherein the first result data word stream is determined as a time-discrete second derivative with time scale TD, and wherein the second result data word stream is determined as a time-discrete second derivative with time scale TD. | ||||||
