A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.

A smart sensor system can include one or more configurable input and output channels, each configurable channel including one or more switches configured to activate the input and/or output and/or to select a type of input and/or output signal, at least one analog-to-digital converter and at least one digital-to-analog converter operatively connected to the one or more switches for the one or more configurable channels, and at least one controller configured to control the configurable channels.

Systems and methods according to one or more embodiments are provided for a high speed digital to analog upconverter that provides for converting a plurality of parallel digital data bits to an analog output signal. In one example, a system includes a decoder circuit configured to receive a plurality of decoder input data bits and provide a plurality of decoded parallel digital data bits. The system also includes a mixer circuit configured to combine each of the decoded parallel digital data bits with a conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other. The system also includes a synchronizer circuit configured to time align the frequency shifted digital data bits. The system further includes a switching network configured to generate an analog output signal in response to the time aligned frequency shifted digital data bits.

Provided is a fuel injection control device capable of improving detection accuracy of a singular point with respect to a characteristic of the fuel injection valve to be equal to or higher than an original time resolution of the A/D conversion, and capable of accurately detecting the singular point. A variable control part 24 variably controls a conversion timing of the A/D conversion part 221 such that the conversion timing of A/D conversion for physical quantity data related to driving of the fuel injection valve 10 is relatively changed, the A/D conversion part 221 acquires a plurality of time series data by performing A/D conversion on the physical quantity data at a conversion timing before change and at a conversion timing after change by the variable control part 24, and a detection part 223 detects a singular point with respect to the characteristic of the fuel injection valve 10 based on the plurality of time series data.

Embodiments of the present invention disclose a power line communications device, and the power line communications device includes a USB interface, a protocol conversion module, a signal conversion module, a coupler, and a power line interface. A first end of the USB interface is connected to a first end of the protocol conversion module, a second end of the protocol conversion module is connected to a first end of the signal conversion module, a second end of the signal conversion module is connected to a first end of the coupler, and a second end of the coupler is connected to a first end of the power line interface. During implementation of the embodiments of the present invention, the USB interface may be used to provide a network signal for a terminal device.

A latch circuit (300) includes an input stage (310), an amplifying stage (MN1, MN2, MP1, MP2) and a clock gating circuit (320). The input stage (310) is arranged for receiving at least a clock signal and a data control signal. The amplifying stage (MN1, MN2, MP1, MP2) is coupled to the input stage (310) and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit (320) is coupled to the amplifying stage (MN1, MN2, MP1, MP2), and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.

There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a closed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

Problem: To prevent that the noise occurs at timing switching between PCM data and DSD data by a simple configuration.

Solution: An AV receiver 1 includes a mute circuit 5 that mutes output from a DAC 4, a detection circuit 6 that detects that a digital audio signal is zero data and supplies a detection signal, a microcomputer 2 that supplies a control signal at timing switching from PCM data to DSD data before switches from PCM mode that the DAC 4 converts PCM data into an analog audio signal to DSD mode that the DAC 4 converts DSD data into the analog audio signal, and an AND circuit 7 that activates the mute circuit 5 in case that the detection signal from the detection circuit 6 and the control signal from the microcomputer 2 are supplied.

The present invention relates to a circuit (100) for stabilizing a voltage on a reference node comprising

- a digital-to-analog converter (10), DAC, comprising an array of capacitors and arranged for receiving an input voltage (V_in) via an input node, a voltage (V_ref,DAC) via a reference node and a DAC code (code_DAC) via a controller node, said DAC code indicating to which capacitors of the array said voltage (V_ref,DAC) is to be applied, and for outputting a DAC output voltage (V_out),

- a capacitive network on the reference node comprising a fixed capacitor (C_ref) arranged to be precharged to an external reference voltage (V_ref) and a variable capacitor (C_aux) arranged to be precharged to an external auxiliary voltage (V_aux) and afterwards to be connected to the reference node,

- a measurement block (40) arranged for measuring the actual voltage on the reference node,

- a calibration block (50) arranged for being fed with the DAC code and the measured actual voltage and for determining an updated setting of the variable capacitor based on the DAC code and the measured actual voltage.