| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 101 | Current mode differential multistage amplifier | JP5393682 | 1982-04-02 | JPS57176814A | 1982-10-30 | DENISU RII ROJIYAASU; ARUBAATO ZABIERU UIDOMAA |
| 102 | Amplifier circuit | JP20386381 | 1981-12-18 | JPS57129507A | 1982-08-11 | DEREKU JIEEMUSU JIENTO |
| 103 | Amplifying circuit | JP3327981 | 1981-03-10 | JPS56140710A | 1981-11-04 | AROISHIUSU YOSEFU NIIMAN; FURANSHISUKASU ADORIANUSU KORU; JIYOBU FURANSHISUKASU PETORASU |
| 104 | JPS5645449B2 - | JP4873975 | 1975-04-23 | JPS5645449B2 | 1981-10-26 | |
| 105 | Improvement of power amplifier | JP674580 | 1980-01-23 | JPS5599808A | 1980-07-30 | BORESUROU MARIAN SOSHIN |
| 106 | JPS5435905B2 - | JP8374274 | 1974-07-19 | JPS5435905B2 | 1979-11-06 | |
| 107 | JPS5415743B2 - | JP1709074 | 1974-02-12 | JPS5415743B2 | 1979-06-16 | |
| 108 | JPS5323063B1 - | JP5203467 | 1967-08-15 | JPS5323063B1 | 1978-07-12 | |
| 109 | JPS50147650A - | JP4873975 | 1975-04-23 | JPS50147650A | 1975-11-26 | |
| 110 | JPS49115636A - | JP1914874 | 1974-02-19 | JPS49115636A | 1974-11-05 | |
| 111 | CONFIGURABLE RADIO FREQUENCY POWER AMPLIFIER AND METHOD THEREOF | US15615899 | 2017-06-07 | US20180358928A1 | 2018-12-13 | Poh-Boon Leong; Chia-Liang (Leon) Lin |
| An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage. | ||||||
| 112 | Configurable radio frequency power amplifier and method thereof | US15615899 | 2017-06-07 | US10153734B1 | 2018-12-11 | Poh-Boon Leong; Chia-Liang (Leon) Lin |
| An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage. | ||||||
| 113 | AMPLIFIER STAGE | US12501526 | 2009-07-13 | US20110006845A1 | 2011-01-13 | Hans Peter Korner |
| An amplifier stage for generating an amplified output signal from an input signal, a mobile device comprising an audio amplifier, and an amplification method for generating an amplified output signal from an input signal using an amplifier stage are described. | ||||||
| 114 | Method and apparatus for improved clock preamplifier with low jitter | US11125960 | 2005-05-10 | US07345528B2 | 2008-03-18 | Alfio Zanchi; Marco Corsi |
| A clock signal preamplifier comprises complementary pairs of differentially coupled transistors, with an output signal coupled to an inverter further comprising a totem-pole arrangement of complementary MOSFET transistors. The input signal to the preamplifier is typically sinusoidal, and the output signal is rectangular. Preferably, the differentially coupled transistors are bipolar, and a pair of diode clamper circuits with bipolar transistors is preferably coupled to the complementary pairs of differentially coupled transistors. A reference voltage source is coupled to the control terminals of the clamper transistors. A reference voltage source, which preferably comprises a totem-pole arrangement of complementary MOSFET transistors with its output node is coupled to its input node, provides a reference voltage for the diode clamper circuits. Preferably, MOSFET transistors of the reference voltage source and MOSFET transistors of like kind of the inverter are configured to have substantially identical threshold voltages. | ||||||
| 115 | Method and apparatus for improved clock preamplifier with low jitter | US11125960 | 2005-05-10 | US20060255859A1 | 2006-11-16 | Alfio Zanchi; Marco Corsi |
| A clock signal preamplifier comprises complementary pairs of differentially coupled transistors, with an output signal coupled to an inverter further comprising a totem-pole arrangement of complementary MOSFET transistors. The input signal to the preamplifier is typically sinusoidal, and the output signal is rectangular. Preferably, the differentially coupled transistors are bipolar, and a pair of diode damper circuits with bipolar transistors is preferably coupled to the complementary pairs of differentially coupled transistors. A reference voltage source is coupled to the control terminals of the damper transistors. A reference voltage source, which preferably comprises a totem-pole arrangement of complementary MOSFET transistors with its output node is coupled to its input node, provides a reference voltage for the diode damper circuits. Preferably, MOSFET transistors of the reference voltage source and MOSFET transistors of like kind of the inverter are configured to have substantially identical threshold voltages. | ||||||
| 116 | Multi-cascode transistors | US10385769 | 2003-03-11 | US06888396B2 | 2005-05-03 | Seyed-Ali Hajimiri; Scott D. Kee; Ichiri Aoki |
| A cascode circuit with improved withstand voltage is provided. The cascode circuit includes three or more transistors, such as MOSFET transistors. Each transistor has a control terminal, such as a gate, and two conduction terminals, such as a drain and a source. The conduction terminals are coupled in series between two output terminals, such as where the drain of each transistor is coupled to the source of another transistor. A signal input is provided to the gate for the first transistor. Two or more control voltage sources, such as DC bias voltages, are provided to the gate of the remaining transistors. The DC bias voltages are selected so as to maintain the voltage across each transistor to a level below a breakdown voltage level. | ||||||
| 117 | Low distortion amplifier | US09915190 | 2001-07-24 | US06600367B2 | 2003-07-29 | Bruce Halcro Candy |
| An electronic amplifier providing very low distortion which includes an output stage with an output error correction stage containing two amplifiers and wherein there are at least four local negative feedback paths, an output of the first amplifier being connected to an input of output stage transistor buffers or output stage transistors through a first network, an output of the second amplifier being connected to an input of output stage transistor buffers or output stage transistors through a second network, where components of the first and second amplifier the local negative feedback paths, first and second networks and output stage transistor buffers are selected to form substantially second order local dominant pole. Also disclosed is the supply of power to said first and second amplifiers from a floating power supply means coupled to either an or the output of the output stage so that the voltage of the floating power supply will follow substantially an output voltage of the output stage. | ||||||
| 118 | Amplifier circuit | US597258 | 1996-02-06 | US5627490A | 1997-05-06 | Koji Sushihara; Takashi Yamamoto; Ikuo Imanishi; Tsuyoshi Nakamura; Michinori Kishimoto; Kenichi Ishida |
| An amplifier circuit for amplifying a change in a resistance value of a magnetic resistance element is formed by connecting a first and a second current mirror circuits having the same structure in cascode, so that a voltage change is amplified without using a capacitive coupling. Hence, a high-pass filter is not created as a parasitic circuit, whereby a gain is maintained high in the low frequency region and a low frequency characteristic is excellent. Further, since control electrodes of transistors which form each current mirror circuit are grounded through the capacitance, a noise is reduced without using a conventional feedback circuit. This eliminates an influence of the feedback circuit over a high frequency characteristic, and therefore, a high frequency characteristic becomes excellent. | ||||||
| 119 | Low consumption multi-stage amplifier, and a vehicle onboard signal receiver having such an amplifier | US410122 | 1995-03-23 | US5530405A | 1996-06-25 | Charles Rydel |
| A multi-stage amplifier of low current consumption, such as an onboard receiver for a motor vehicle for receiving telecontrol systems for opening the doors or interrogation signals for the alarm system of the vehicle, has the polarising networks for the amplification stages connected in series in such a way as to reduce the power consumption of the circuitry in the static state. The amplifier stages are connected in series on the polarising bridge in the static state, and in the dynamic state they are connected in cascade. The output of the first stage is connected to the input of the next stage through an impedance matching reactance. In another aspect, gain is controlled by injection/extraction of current between the output terminal of the amplifier and an injection/extraction terminal on the input of the first stage. | ||||||
| 120 | Cascode mirror video amplifier | US521440 | 1990-05-10 | US4973890A | 1990-11-27 | Francois Desjardins |
| A cascode mirror video amplifier for generating equal amplitude and opposite phase signals for driving a cathode and control grid of a cathode ray tube. The video amplifier comprises a pair of common base amplifiers connected via equal valued resistances to a pair of opposite polarity power sources. A common emitter amplifier is connected intermediate the pair of cascaded common base amplifiers and functions as a voltage control current source for receiving an input signal and in response generating a common current signal within each of the pair of common base amplifiers such that equal amplitude and opposite phase voltage signals are generated across the respective resistances. A pair of emitter follower stages apply the voltage across the resistance pair to the electron source cathode and control grid respectively while isolating the load capacitance of the cathode ray tube from each of the common base amplifiers. | ||||||
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