子分类：
- H03F3/005： .{使用开关电容器的,例如,动态放大器;用开关电容器作为差分放大器中的电阻器 (H03F3/45 优先)}
- H03F3/02： .只带有电子管的(其后各小组优先)
- H03F3/04： .只带有半导体器件的(其后各小组优先)
- H03F3/181： .低频放大器,例如音频前置放大器
- H03F3/189： .高频放大器,例如射频放大器
- H03F3/20： .功率放大器,例如乙类放大器,丙类放大器(H03F3/26至H03F3/30优先)
- H03F3/26： .推挽放大器;其所用分相器(双单端推挽配置或其所用的分相器入H03F3/30)
- H03F3/30： .单端推挽{(SEPP)}放大器{(单端传感放大器入G11C7/067)};其所用分相器
- H03F3/34： .各级均用直流耦合的直流放大器(H03F3/45优先)
- H03F3/38： .输入端有调制器、输出端有解调器的直流放大器;专门用于此种放大器的调制器或解调器(开关电容放大器入H03F3/005;一般调制器H03C;一般解调器入H03D;一般脉冲幅度调制入H03K7/02;一般脉冲幅度解调入H03K9/02)
- H03F3/42： .有两个或两个以上放大元件的放大器,这些元件与负载串联构成直流通道,每个元件的控制极至少由部分输入信号激励,例如所谓“图腾柱"放大器
- H03F3/45： .差分放大器(差分检测放大器入 G11C7/062)
- H03F3/46： .来复式放大器{(反射放大器入H03F3/608)}
- H03F3/50： .放大器的输入或输出连结到一个放大元件的输入和输出电路所共有的阻抗,例如阴极跟随器
- H03F3/54： .应用电子管或半导体器件中电子渡越时间效应的放大器(参量放大器入H03F7/00;固态行波器件入H01L45/02)
- H03F3/60： .耦合网络具有分布常数的放大器,例如带有波导谐振器(H03F3/54优先)
- H03F3/62： .双向放大器
- H03F3/66： .产生一个频率的振荡并能同时放大另一频率的信号的放大器
- H03F3/68： .放大器的组合,例如用于立体声的多通道放大器{(组合使用多个半导体放大器的功率放大器入 H03F3/211;耦合网络带有分布常数的放大器的组合入 H03F3/602)}
- H03F3/70： .电荷放大器
- H03F3/72： .选通放大器,即利用控制信号使其工作或不工作的放大器
| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 使用多电平脉冲宽度调制的音频放大器 | CN201180063192.5 | 2011-10-27 | CN103329431B | 2016-09-14 | 米克尔·霍耶尔比 |
| 本发明一个方面涉及一种D类音频放大器，其具有支持应用于扬声器负载的诸如3电平、4电平或5电平脉冲宽度或脉冲密度调制输出信号的多电平输出信号的改进型输出驱动器拓扑。本发明的D类音频放大器特别适合大批量消费音频应用和解决方案。 | ||||||
| 2 | 开关电流源电路和方法 | CN201410093057.0 | 2014-03-13 | CN104052283B | 2017-04-12 | 马克·伯克豪特 |
| 一种开关电流源，其中对在驱动输出晶体管的栅极时使用的参考电压值进行采样和存储。使用向电流感测晶体管馈电的参考电流源来得到参考电压。当输出晶体管截止时将电流感测晶体管截止，使得参考电流源不会消耗功率。然后，可以短时间使用较大的参考电流Iref。 | ||||||
| 3 | 具有胳肢脉冲注入的电源 | CN201280023341.X | 2012-04-04 | CN103534939B | 2016-11-09 | K·B·德尔帕帕; M·纽斯鲍姆; A·费伦兹 |
| 一种电源将一系列“胳肢”脉冲注入到脉冲宽度调制（PWM）控制器中，以诱导该控制器以最小开关频率生成PWM脉冲，优选地，该最小开关频率是超声波的（尤其对于音频应用）。开关频率还可以被选择或控制为使得其避免电源中的谐振。“胳肢”脉冲可以通过对PWM控制器定时的相同时钟来计时，并且它们可以被整形，以帮助确保电源在低负载状况期间维持某种调整。 | ||||||
| 4 | 开关电流源电路和方法 | CN201410093057.0 | 2014-03-13 | CN104052283A | 2014-09-17 | 马克·伯克豪特 |
| 一种开关电流源，其中对在驱动输出晶体管的栅极时使用的参考电压值进行采样和存储。使用向电流感测晶体管馈电的参考电流源来得到参考电压。当输出晶体管截止时将电流感测晶体管截止，使得参考电流源不会消耗功率。然后，可以短时间使用较大的参考电流Iref。 | ||||||
| 5 | 具有胳肢脉冲注入的电源 | CN201280023341.X | 2012-04-04 | CN103534939A | 2014-01-22 | K·B·德尔帕帕; M·纽斯鲍姆; A·费伦兹 |
| 一种电源将一系列“胳肢”脉冲注入到脉冲宽度调制（PWM）控制器中，以诱导该控制器以最小开关频率生成PWM脉冲，优选地，该最小开关频率是超声波的（尤其对于音频应用）。开关频率还可以被选择或控制为使得其避免电源中的谐振。“胳肢”脉冲可以通过对PWM控制器定时的相同时钟来计时，并且它们可以被整形，以帮助确保电源在低负载状况期间维持某种调整。 | ||||||
| 6 | 使用多电平脉冲宽度调制的音频放大器 | CN201180063192.5 | 2011-10-27 | CN103329431A | 2013-09-25 | 米克尔·霍耶尔比 |
| 本发明一个方面涉及一种D类音频放大器，其具有支持应用于扬声器负载的诸如3电平、4电平或5电平脉冲宽度或脉冲密度调制输出信号的多电平输出信号的改进型输出驱动器拓扑。本发明的D类音频放大器特别适合大批量消费音频应用和解决方案。 | ||||||
| 7 | 電子回路 | JP2013154795 | 2013-07-25 | JP6244714B2 | 2017-12-13 | 檀上 匠 |
| 8 | レギュレータ | JP2013012933 | 2013-01-28 | JP5997620B2 | 2016-09-28 | 西川 一郎; 後藤 祐一 |
| 9 | オーディオ出力回路およびそれを用いた電子機器、オーディオ用集積回路 | JP2012053632 | 2012-03-09 | JP5969779B2 | 2016-08-17 | 胸永 秀樹; 小野寺 武志 |
| 10 | POWER SUPPLY WITH TICKLE PULSE INJECTION | EP12716853.2 | 2012-04-04 | EP2695295B1 | 2017-07-12 | DELPAPA, Kenneth B.; NUSSBAUM, Michael; FERENCZ, Andrew |
| A power supply injects a series of “tickle” pulses into a pulse width modulated (PWM) controller to induce the controller to generate PWM pulses at a minimum switching frequency, preferably one that is super-sonic (especially for audio applications). The switching frequency may also be selected or controlled such that it avoids resonances in the power supply. The “tickle” pulses may be clocked by the same clock that times the PWM controller, and they may be shaped to help ensure that the power supply maintains some regulation during low-load conditions. | ||||||
| 11 | Switchable current source circuit and method | EP13158925.1 | 2013-03-13 | EP2779452A1 | 2014-09-17 | Berkhout, Marco |
a switchable current source in which a reference voltage value to be used in driving the gate of an output transistor is sampled and stored. The reference voltage is derived using a reference current source which feeds a current sensing transistor. The current sensing transistor is turned off when the output transistor is turned off, so that the reference current source then does not consume power. A large reference current Iref can then be used for a short time.
|
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| 12 | AUDIO AMPLIFIER USING MULTI-LEVEL PULSE WIDTH MODULATION | EP11775967.0 | 2011-10-27 | EP2633621A1 | 2013-09-04 | HØYERBY, Mikkel |
| The present invention relates in one aspect to a class D audio amplifier with improved output driver topology supporting multi-level output signals such as 3-level, 4-level or 5-level pulse width or pulse density modulated output signals for application to a loudspeaker load. The present class D audio amplifiers are particularly well-suited for high-volume consumer audio applications and solutions. | ||||||
| 13 | Clamping audio signal paths | US15439323 | 2017-02-22 | US10142721B2 | 2018-11-27 | Rupesh Khare |
| This application describes methods and apparatus for selectively clamping a signal path (106) for an analog audio signal to a clamp voltage, e.g. ground. Voltage clamping circuitry (200) is disclosed having a first switching device (201) in series with a second switching device (202) between a node of the signal path and the clamp voltage. The clamping circuitry is configured to be operable in: a first state where the first and second switching devices are both on to electrically connect the signal path to the clamp voltage; and also a second state to electrically disconnect the signal path from the clamp voltage. In the second state one of the first and second switching devices is configured to block conduction when the voltage at said node of the signal path is positive and the other switching device is configured to block conduction when the voltage at said node of the signal path is negative. | ||||||
| 14 | System for and method of reducing transmit signal distortion | US15363841 | 2016-11-29 | US10141960B2 | 2018-11-27 | Loke K. Tan; Takayuki Hayashi; Lin He; Giuseppe Cusmai; Chun-ying Chen |
| Systems and methods relate to providing a transmit signal. The transmit signal can be provided in a transmitter circuit including a main pre-equalizer, a main power amplifier in communication with the main pre-equalizer, a replica pre-equalizer, and a replica power amplifier in communication with the replica pre-equalizer. The replica preamplifier is in communication with the main pre-equalizer, and control signals are provided to the main pre-equalizer to reduce distortion. The control signals are provided in response to an output signal of the replica power amplifier. | ||||||
| 15 | PARALLEL USE OF SERIAL CONTROLS IN IMPROVED WIRELESS DEVICES AND POWER AMPLIFIER MODULES | US15634841 | 2017-06-27 | US20180019772A1 | 2018-01-18 | Matthew Lee Banowetz; Philip H. Thompson; Edward James Anthony; James Henry Ross |
| A power amplifier module can include one or more switches, a coupler module, input signal pins, and a controller having first and second output terminals. The input signal pins can receive a voltage input/output signal, a clock input signal, and a data input signal. The controller can (i) set a mode of the one or more switches using a synchronous communication protocol in which the controller outputs a synchronous clock signal on the first output terminal and a data signal on the second output terminal, when the power amplifier module is in a first operating mode, or (ii) set a mode of the coupler module using an asynchronous communication protocol in which the controller outputs a first asynchronous control signal on the first output terminal and a second asynchronous control signal on the second output terminal, when the power amplifier module is in a second operating mode. | ||||||
| 16 | AUDIO AMPLIFIER USING MULTI-LEVEL PULSE WIDTH MODULATION | US15344151 | 2016-11-04 | US20170117851A1 | 2017-04-27 | Mikkel Høyerby |
| The present invention relates in one aspect to a class D audio amplifier with improved output driver topology supporting multi-level output signals such as 3-level, 4-level or 5-level pulse width or pulse density modulated output signals for application to a loudspeaker load. The present class D audio amplifiers are particularly well-suited for high-volume consumer audio applications and solutions. | ||||||
| 17 | PARALLEL USE OF SERIAL CONTROLS IN IMPROVED WIRELESS DEVICES AND POWER AMPLIFIER MODULES | US15280885 | 2016-09-29 | US20170093559A1 | 2017-03-30 | Matthew Lee Banowetz; Philip H. Thompson; Edward James Anthony; James Henry Ross |
| A power amplifier module can include one or more switches, a coupler module, input signal pins, and a controller having first and second output terminals. The input signal pins can receive a voltage input/output signal, a clock input signal, and a data input signal. The controller can (i) set a mode of the one or more switches using a synchronous communication protocol in which the controller outputs a synchronous clock signal on the first output terminal and a data signal on the second output terminal, when the power amplifier module is in a first operating mode, or (ii) set a mode of the coupler module using an asynchronous communication protocol in which the controller outputs a first asynchronous control signal on the first output terminal and a second asynchronous control signal on the second output terminal, when the power amplifier module is in a second operating mode. | ||||||
| 18 | Fast turn on system for a synthesized source signal | US13833324 | 2013-03-15 | US09172381B2 | 2015-10-27 | Mark M. Cloutier; Greg Bachmanek; Tolga Pamir |
| A fast turn on compensation system for a synthesized signal source includes a synthesized signal source coupled to a power supply and configured to generate a phase stable radio frequency (RF) output signal. A mute amplifier is coupled to the synthesized signal source and the power supply. A dummy amplifier is coupled to the mute amplifier and the power supply. A mute controller is coupled to the mute amplifier and the dummy amplifier, the mute controller is responsive to an enable signal and configured to enable the dummy amplifier and disable the mute amplifier when no RF output signal is being generated and disable the dummy amplifier and enable the mute amplifier when the RF output signal is being generated such that total power supply current delivered to the synthesized signal source and the dummy amplifier or mute amplifier is approximately constant before, during, and after enabling the mute amplifier to reduce phase disturbance of the RF output signals. | ||||||
| 19 | Electronic circuit | US14321644 | 2014-07-01 | US09154120B2 | 2015-10-06 | Takumi Danjo |
| An electronic circuit includes: a pair of first transistors in which a first control signal is inputted to at least one of a first control terminal; a comparator circuit that sets electric potentials of a pair of differential output terminals based on an electric current flowing through the pair of first transistors; second transistors that are coupled in series in a path between an electric power source and a node from at least one of the pair of differential output terminals and between the corresponding pair of first transistors, and having a second control terminals to which a second control signal is inputted; first switches that are respectively coupled in series to the second transistors in the path and that are turned ON in synchronization with a clock signal; and a generation circuit that generates the second control signal based on the clock signal. | ||||||
| 20 | Low dropout regulator having differential circuit with X-configuration | US13931347 | 2013-06-28 | US09134740B2 | 2015-09-15 | Ichiro Nishikawa; Yuichi Goto |
| A regulator includes a first transistor, a first bias circuit, a second bias circuit, a differential circuit having second to fifth transistors, and a current mirror circuit. The first transistor outputs an output voltage lower than the input voltage. The first bias circuit generates a first bias voltage lower than a reference voltage. The second bias circuit generates a second bias voltage lower than a feedback voltage relating to the output voltage. The second transistor into which the reference voltage is inputted and the third transistor into which the feedback voltage is inputted are a pair of differential transistors. The fourth transistor is complementarily connected to the second transistor. The fifth transistor is complementarily connected to the third transistor. The differential circuit outputs a comparison signal to the first transistor. The current mirror circuit is connected to the second and third transistors. | ||||||
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