| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | Stacked PA power control | US15451184 | 2017-03-06 | US09960737B1 | 2018-05-01 | David Kovac |
| Systems, methods and apparatus for efficient power control of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift in output power of the RF amplifier. | ||||||
| 42 | RF amplifier operational in different power modes | US14557897 | 2014-12-02 | US09935585B2 | 2018-04-03 | Alireza Shirvani |
| Embodiments of a radio frequency (RF) amplification are disclosed. The RF amplification device includes a first RF amplification circuit, a second RF amplification circuit, and power control circuitry operable in a first power mode and a second power mode. The first RF amplification circuit has a cascode amplifier stage configured to amplify an RF signal. The cascode amplifier stage has an input transistor and a cascode output transistor that are stacked in cascode. The second RF amplification circuit is configured to amplify the RF signal. The power control circuitry is configured to bias the first cascode output transistor so that the first cascode output transistor operates in a saturation region in the first power mode and bias the first cascode output transistor so that the first cascode output transistor operates in a triode region in the second power mode. The second RF amplification circuit is assisted without introducing additional loading. | ||||||
| 43 | AMPLIFIER | US15618446 | 2017-06-09 | US20170359046A1 | 2017-12-14 | Ken Wakaki; Daisuke Watanabe |
| An amplifier according to an embodiment of the present invention includes a first transistor and a second transistor that are connected between a ground point and a power supply. A control terminal of the first transistor is connected to an input terminal. A first terminal of the first transistor is connected to the ground point. A second terminal of the second transistor is connected to an output terminal. The amplifier further includes an impedance element and a variable resistance unit. The impedance element is connected between the second terminal of the second transistor and the power supply. The variable resistance unit is connected between the second terminal of the first transistor and the first terminal of the second transistor. | ||||||
| 44 | Switching circuit | US15195707 | 2016-06-28 | US09748951B2 | 2017-08-29 | Xiaoqiang Zhang; Mark Ingels |
| A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. The conversion circuit includes a second input terminal for receiving a bias voltage signal. The conversion circuit includes an output terminal for outputting a current. The conversion circuit includes a first and a second switch transistor connected to the first input terminal for receiving the digital signal. The conversion circuit includes a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal. The conversion circuit further includes a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor. The conversion circuit further includes a second branch, wherein the second current source transistor is connected to the output terminal via the second switch transistor. | ||||||
| 45 | Bias control for stacked transistor configuration | US14626833 | 2015-02-19 | US09716477B2 | 2017-07-25 | Poojan Wagh; Joseph Golat; David Kovac; Jeffrey A. Dykstra; Chris Olson |
| Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented. | ||||||
| 46 | Current-mode power amplifier | US14950295 | 2015-11-24 | US09712115B2 | 2017-07-18 | Niranjan Talwalkar |
| A current-mode power amplifier is disclosed. In some embodiments, the power amplifier may include a first cascode transistor pair including a first transfer function coupled to a second cascode transistor pair including a second transfer function. The first transfer function may be an inverse of the second transfer function. The current-mode power amplifier may also include an inductive-capacitive (LC) resonant circuit to reduce the effects of gate capacitances of the first cascode transistor pair and the second cascode transistor pair. In some embodiments, the current-mode power amplifier may include a bias current controller. The bias current controller may adjust transistor bias currents based, at least in part, on an input signal received by the current-mode power amplifier. | ||||||
| 47 | SWITCHING CIRCUIT | US15195707 | 2016-06-28 | US20170005654A1 | 2017-01-05 | Xiaoqiang Zhang; Mark Ingels |
| A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. The conversion circuit includes a second input terminal for receiving a bias voltage signal. The conversion circuit includes an output terminal for outputting a current. The conversion circuit includes a first and a second switch transistor connected to the first input terminal for receiving the digital signal. The conversion circuit includes a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal. The conversion circuit further includes a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor. The conversion circuit further includes a second branch, wherein the second current source transistor is connected to the output terminal via the second switch transistor. | ||||||
| 48 | Broadband amplifier topology with current shutdown | US13920258 | 2013-06-18 | US09444416B1 | 2016-09-13 | Ian M. Bisby |
| An apparatus includes a first depletion-mode transistor, a first enhancement-mode transistor, and a pull down switch. The first depletion-mode transistor has a common source configuration. The first enhancement-mode transistor has a common gate configuration. The first depletion-mode transistor and the first enhancement-mode transistor are coupled in a cascode arrangement. The pull down switch is operatively coupled between a gate of the enhancement-mode transistor and a circuit ground. | ||||||
| 49 | Low voltage multi-stage amplifier | US13793933 | 2013-03-11 | US09438189B2 | 2016-09-06 | Vijayakumar Dhanasekaran |
| A low voltage multi-stage amplifier is described. The low voltage multi-stage amplifier includes one or more prior stages. The low voltage multi-stage amplifier also includes a supply stage. The low voltage multi-stage amplifier further includes an output stage that operates with a supply voltage as low as a sum of a threshold voltage of a first transistor in the output stage and a saturation voltage of a second transistor of the supply stage. The supply stage supplies the output stage. | ||||||
| 50 | LOW POWER MULTI-STACKED POWER AMPLIFIER | US14286877 | 2014-05-23 | US20150340992A1 | 2015-11-26 | Victor Korol; Shu-Hsien Liao |
| An apparatus includes a plurality of stacked transistors in a multi-stacked power amplifier. At least one transistor of the plurality of stacked transistors is configured to operate in a first mode and in a second mode. The at least one transistor of the plurality of stacked transistors is configured to be biased by a low power biasing network to operate in the first mode. | ||||||
| 51 | BIAS CIRCUITS AND METHODS FOR STACKED DEVICES | US14298665 | 2014-06-06 | US20150244322A1 | 2015-08-27 | Joonhoi Hur; Paul Joseph Draxler; Calogero Presti; Marco Cassia |
| Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced. | ||||||
| 52 | Electronic circuit and electronic circuit arrangement | US12690009 | 2010-01-19 | US08994449B2 | 2015-03-31 | Uwe Hodel; Stephan Leuschner; Jan-Erik Mueller |
| In accordance with one exemplary embodiment, an electronic circuit is provided, wherein the electronic circuit comprises a first transistor and also a second transistor coupled in series with the first transistor. Furthermore, the electronic circuit comprises a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic circuit. | ||||||
| 53 | ADJUSTABLE GAIN FOR MULTI-STACKED AMPLIFIERS | US13678923 | 2012-11-16 | US20140139288A1 | 2014-05-22 | Jeongwon Cha; Chang-Ho Lee; Aristotele Hadjichristos |
| Techniques for providing adjustable gain in an amplifier. In an aspect, a composite amplifier having adjustable gain includes a plurality of amplifiers coupled in parallel, wherein each of the amplifiers may be turned on or off to adjust the overall gain of the composite amplifier. Each amplifier may include an input transistor and at least two cascode transistors. To turn each amplifier off, the gate voltage of a second or lowermost cascode transistor coupled to the input transistor may be grounded, and the gate voltage of a first cascode transistor coupled to the output voltage may be coupled to a first turn-off voltage to reduce the drain-to-gate voltage drop across the first cascode transistor. Further aspects provide for decoupling a capacitor coupled to the gates of the cascode transistors from AC ground when the amplifier is turned off | ||||||
| 54 | Circuit and Power Amplifier | US13628904 | 2012-09-27 | US20130082782A1 | 2013-04-04 | Stephan Leuschner; Jan-Erik Mueller |
| A cascode circuit includes a first transistor and a second transistor. The first transistor and the second transistor are connected to make a cascode. In addition, the circuit has a block capacitance which is connected between a control terminal of the second transistor and a source terminal of the first transistor. In addition, the circuit has a feedback element which is connected between a drain terminal of the second transistor and a control terminal of the first transistor. | ||||||
| 55 | Distributed amplifier with improved stabilization | US13385772 | 2012-03-06 | US20120229216A1 | 2012-09-13 | Keith Benson |
| A distributed amplifier with improved stabilization includes an input transmission circuit, an output transmission circuit, at least one cascode amplifier coupled between said input and output transmission circuits. Each cascode amplifier includes a common-gate configured transistor coupled to the output transmission circuit, and a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor. The distributed amplifier also includes a non-parasitic resistance and capacitance coupled in series between a drain and a gate of at least one of the common-gate configured transistors for increasing the amplifier stability. | ||||||
| 56 | Low noise cascode amplifier | US12457927 | 2009-06-25 | US08040188B2 | 2011-10-18 | Bo-Jr Huang; Huei Wang |
| The present invention relates to a low noise cascode amplifier comprising a first transistor, a second transistor, a third transistor, a first inductor, and a second inductor. Furthermore, the first transistor can connect with the second transistor via the first inductor, and the second transistor can connect with the third transistor via the second inductor; thereby, a cascode device can be formed. The inductor and the parasitic capacitances can resonate at high frequency, so that the noise figure of the cascode amplifier can be reduced. | ||||||
| 57 | High-linearity low noise amplifier | US12422430 | 2009-04-13 | US08018288B2 | 2011-09-13 | Jon S. Duster; Stewart S. Taylor |
| Embodiments of a high-linearity low-noise amplifier (LNA) are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier. The cascode amplifier may include integrated notch filters to attenuate undesired signals. The cascode amplifier may operate from a large power supply when blockers are present to avoid voltage swing compression at its output. The cascode amplifier may be biased and designed to operate in a class AB mode to produce linear output current to avoid current compression or excessive current expansion. | ||||||
| 58 | Cascode CMOS RF power amplifier with programmable feedback cascode bias under multiple supply voltages | US12428616 | 2009-04-23 | US07786807B1 | 2010-08-31 | Mingyuan Li; Ali Afsahi; Arya Reza Behzad |
| A Radio Frequency (RF) cascode power amplifier operates with differing battery supply voltages. A transconductance stage has a transistor with an RF signal input at its gate. A cascode stage has at least one cascode transistor, the cascode stage coupled in series with the transconductance stage between a battery voltage node and ground, the cascode stage having an RF signal output at the battery voltage node and at least one bias input to the at least one cascode transistor. Cascode bias feedback circuitry applies fixed bias voltage(s) to the at least one two bias inputs for a low battery voltage and applies feedback bias voltage(s) to the at least two bias inputs for a high battery voltage, the feedback bias voltage(s) based upon a voltage of the battery voltage node. More than two differing battery supply voltages are supported. | ||||||
| 59 | Accurate cascode bias networks | US11098904 | 2005-04-04 | US20060197586A1 | 2006-09-07 | Arthur Kalb |
| Bias networks are provided for accurate generation of biases of cascode transistor arrangements. Network embodiments generate a voltage that accurately biases the transistor of a cascode arrangement at a selected point in its saturation region and this voltage is accurately transferred to the drain of a transistor via the gate-to-source voltage drops of a pair of gate-coupled transistors. | ||||||
| 60 | Switchless Multi Input Stacked Transistor Amplifier Tree Structure | US15846055 | 2017-12-18 | US20190190468A1 | 2019-06-20 | Khushali Shah; Haopei Deng |
| Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage. | ||||||
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