| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 141 | Interdigitated layout methodology for amplifier and H-bridge output stages | US10656451 | 2003-09-05 | US20050051853A1 | 2005-03-10 | David Baum; Rodney Burt |
| A complementary output stage in integrated circuit includes a P-channel transistor (MP1) the segmented into a first group of sections (MP1-1,2 . . . 12) and an N-channel transistor (MN1) segmented into a second group of sections (MN1-1,2 . . . 12). The sections of the first group are disposed in a plurality of N-type well regions (35), respectively, and the sections of the second group are disposed in a plurality of P-type well regions (36), respectively. The sections of the first group are alternately located with respect to the sections of the second group so as to form an interdigitated output stage area of the integrated circuit including the P-channel transistor (MP1) and the N-channel transistor (MN1) so that the higher amount of heat normally generated in the N-channel transistor is dissipated over the entire interdigitated output stage area and reduces peak temperatures in the N-channel transistor. | ||||||
| 142 | Radio frequency power amplifier module | US10822781 | 2004-04-13 | US06842076B2 | 2005-01-11 | Akira Kuriyama; Masami Ohnishi |
| An object of the present invention is to provide a radio-frequency power amplifier of multi stage amplifying method that is designed to reduce instability of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby operate stably. Another object of the present invention is to provide a radio frequency power amplifier that is designed to reduce distortion of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby provide high efficiency. The above objects can be achieved by providing a first interconnection connected to a terminal for supplying a voltage for collector driving to a power amplifying transistor, a second interconnection connected to a terminal for supplying a voltage for collector driving to a second transistor controlling a base bias voltage of the above transistor, and one or more ground parts for electromagnetic shield, wherein the first interconnection and the second interconnection are separated by one or more of the ground parts for electromagnetic shield. | ||||||
| 143 | Radio frequency power amplifier module | US10822781 | 2004-04-13 | US20040189400A1 | 2004-09-30 | Akira Kuriyama; Masami Ohnishi |
| An object of the present invention is to provide a radio frequency power amplifier of multi stage amplifying method that is designed to reduce instability of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby operate stably. Another object of the present invention is to provide a radio frequency power amplifier that is designed to reduce distortion of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby provide high efficiency. The above objects can be achieved by providing a first interconnection connected to a terminal for supplying a voltage for collector driving to a power amplifying transistor, a second interconnection connected to a terminal for supplying a voltage for collector driving to a second transistor controlling a base bias voltage of the above transistor, and one or more ground parts for electromagnetic shield, wherein the first interconnection and the second interconnection are separated by one or more of the ground parts for electromagnetic shield. | ||||||
| 144 | Voltage buffer for capacitive loads | US10356098 | 2003-01-30 | US20040150464A1 | 2004-08-05 | Shahzad Khalid |
| A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is connected to have the same control gate level as the transistor in the feedback loop and provide an output voltage based on the reference input voltage. The output voltage is dependent upon the input voltage, but the load is removed from the feedback loop. By removing the load from the feedback loop, the loop is stabilized with only a very small or no compensating capacitor, allowing the quiescent current of the buffer to be reduced and the settling time to be improved. One preferred use of the present invention is to drive the data storage elements of a non-volatile memory. | ||||||
| 145 | Amplifier for FM antennas | US10376747 | 2003-02-28 | US20030146793A1 | 2003-08-07 | Katsushiro Ishibayashi |
| An amplifier comprising a transformer and a plurality of FETs, for example, three FETs. An input terminal, which receives a signal from an FM antenna, is connected to one end of the primary winding of the transformer. A power-supply voltage is applied to one end of the secondary winding of the transformer. A given middle part of the secondary winding is connected to an output terminal. The transistors have their source connected in parallel to the other end of the primary winding of the transformer, their drains connected in parallel to the other end of the secondary winding, and their gates connected to the ground. | ||||||
| 146 | Amplifier circuit | US10153868 | 2002-05-24 | US20020175762A1 | 2002-11-28 | Jesper Riishoj; Peter Dam Lerke |
| An amplifier circuit includes a bias control feedback loop. A sensing transistor (108) is matched to one or more power transistors (101a, 101b, 101c) and is correspondingly biased. The difference between collector voltage of the sensing transistor (108) and a reference voltage amplified by a differential amplifier (111, 114) to provide the base bias voltage for the power transistors (101a, 101b, 101c) and the sensing transistor (105). The gain of the amplifier is controlled by applying a control voltage to a resistor (110) connected to the collector of the sensing transistor (105). | ||||||
| 147 | Semiconductor integrated circuit | US948033 | 1997-10-09 | US5903178A | 1999-05-11 | Kazuo Miyatsuji; Daisuke Ueda |
| A drain and a source of a field-effect transistor are connected to first and second signal terminals, respectively. A first control terminal is connected to a gate. A first resistor is interposed between the gate and the first control terminal. Capacitors are interposed between the source/drain and the first and second signal terminals, respectively. A control terminal is connected to at least one of the source/drain via a second resistor. High frequency signals supplied through the first signal terminal is sent through the field-effect transistor and outputted through the second signal terminal, and a quantity of the transmitted high frequency signals is controlled by a control voltage signal applied across the first and second control terminals. This structure provides a high frequency semiconductor integrated circuits which reduces a power consumption and an occupied area, increases a switchable power, suppresses output distortion, and simplifies a peripheral circuit. | ||||||
| 148 | Bipolar transistor circuit | US710973 | 1996-09-24 | US5625205A | 1997-04-29 | Noboru Kusama |
| In an NPN type bipolar transistor, by employing AlGaAs or InGaAs having greater band gap than silicon, for an emitter and a base, doping amount of the emitter can be made smaller than that of the base to permit improvement of reverse withstanding voltage between the base and the emitter. Therefore, B class or C class bias can be used in a microwave band to improve efficiency. | ||||||
| 149 | Reel motor preamplifier | US962278 | 1978-11-20 | US4177433A | 1979-12-04 | Robert J. Christopher; Robert L. Schaaf |
| A high voltage/high current circuitry includes a push-pull voltage amplification stage connected in tandem with a parallel connected push-pull current amplification stage. For the voltage amplification stage a pair of bipolar operational amplifiers are connected in parallel and operate in a push-pull manner. A pair of switching means are positioned at the output of each of the bipolar operational amplifiers while the outputs of the amplifiers are connected to the inputs through a current gain regulating means, an isolation means and a voltage divider means. | ||||||
| 150 | Amplifier with over-current protection | US553636 | 1975-02-27 | US3967207A | 1976-06-29 | Carl Franklin Wheatley, Jr. |
| PNP composite transistors connected as commonemitter amplifiers each comprise a PNP pre-amplifier transistor in direct coupled cascade with a plurality of parallelled NPN transistors. The emitter-electrode of the PNP transistor is connected to a sensing resistor in the collector path of one of these NPN transistors, causing the "base-to-emitter" potential of the composite transistor to increase if its "emitter" current exceeds a threshold current. By clamping this base-to-emitter potential if it exceeds a predetermined potential, the output current of the composite transistor is prevented from becoming excessive. This predetermined potential is controlled as a function of composite transistor temperature and supply potential to provide the required degree of over-current protection for these particular conditions. | ||||||
| 151 | APPARATUS AND METHODS FOR OSCILLATION SUPPRESSION OF CASCODE POWER AMPLIFIERS | US15922134 | 2018-03-15 | US20180294781A1 | 2018-10-11 | John William Mitchell Rogers |
| Apparatus and methods for oscillation suppression of cascode power amplifiers are provided herein. In certain implementations, a power amplifier system includes a cascode power amplifier including a plurality of transconductance devices that operate in combination with a plurality of cascode devices to amplify a radio frequency input signal. The power amplifier system further includes a bias circuit that biases the plurality of cascode devices with two or more bias voltages that are decoupled from one another at radio frequency to thereby inhibit the cascode power amplifier from oscillating. | ||||||
| 152 | POWER AMPLIFIER | US15800779 | 2017-11-01 | US20180287561A1 | 2018-10-04 | Hyeon Seok HWANG; Jong Soo LEE; Seung Chul PYO |
| A power amplifier includes an amplifying circuit configured to amplify an input signal and comprising transistors, which may be disposed in parallel with one another and divided into a first group of transistors and a second group of transistors. The power amplifier also includes a bias circuit configured to supply bias power to one of the transistors of the first group and the transistors of the second group. | ||||||
| 153 | RF AMPLIFIER | US15865145 | 2018-01-08 | US20180198420A1 | 2018-07-12 | Marco D'Avino; Mark Pieter van der Heijden; Michel Wilhelmus Arnoldus Groenewegen; Leonardus Cornelis Nicolaas de Vreede |
| An RF amplifier is described including an input, an output, a parallel arrangement of a first branch and at least one further branch, each branch comprising a bipolar transistor in a degenerative emitter configuration having a base coupled to the input, a collector coupled to a common collector node, and an emitter degeneration impedance arranged between the emitter and a common rail. The common collector node is coupled to the output, the base of the first branch bipolar transistor is biased at a first bias voltage and the base of the at least one further branch bipolar transistor is biased at a bias voltage offset from the first bias voltage. In operation of the RF amplifier a IM3 distortion current output by the first branch bipolar transistor is in antiphase to a IM3 distortion current output by the at least one further branch bipolar transistor. | ||||||
| 154 | Voltage sampler driver with enhanced high-frequency gain | US15415831 | 2017-01-25 | US10003315B2 | 2018-06-19 | Armin Tajalli |
| Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair. | ||||||
| 155 | Symmetric Linear Equalization Circuit with Increased Gain | US15237171 | 2016-08-15 | US20170040965A1 | 2017-02-09 | Armin Tajalli |
| Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals. | ||||||
| 156 | Operational amplifier | US14549553 | 2014-11-21 | US09436023B2 | 2016-09-06 | Wei-Ta Chiu |
| An operational amplifier comprises a first metal-oxide-semiconductor field effect transistor (MOSFET), comprising a first drain, a first gate and a first source; a second MOSFET, comprising a second drain, a second gate and a second source, the second source coupled to the first source of the first MOSFET; and a bias source, coupled between a first specific level and the first source of the first MOSFET and the second source of the second MOSFET; wherein the first MOSFET and the second MOSFET are depletion-type. | ||||||
| 157 | Operational Amplifier | US14549553 | 2014-11-21 | US20150333714A1 | 2015-11-19 | Wei-Ta Chiu |
| An operational amplifier comprises a first metal-oxide-semiconductor field effect transistor (MOSFET), comprising a first drain, a first gate and a first source; a second MOSFET, comprising a second drain, a second gate and a second source, the second source coupled to the first source of the first MOSFET; and a bias source, coupled between a first specific level and the first source of the first MOSFET and the second source of the second MOSFET; wherein the first MOSFET and the second MOSFET are depletion-type. | ||||||
| 158 | Switching circuit and envelope signal amplifier | US13643978 | 2011-03-28 | US08878604B2 | 2014-11-04 | Takashi Ohira; Kazuyuki Wada; Mitsutoshi Nakata; Kazushi Sawada; Satoshi Hatsukawa; Nobuo Shiga; Kazuhiro Fujikawa |
| A switching circuit according to one embodiment has: N switching elements; a connection circuit including N−1 first inductance elements that are connected in series; a second inductance element; and N third inductance elements. Control terminals of the N switching elements are connected to ends of the connection circuit and connection contacts, respectively. One end of the second inductance element is connected to a power supply. The N third inductance elements electrically connects one ends of the N switching elements and the other end of the second inductance element with each other, respectively. | ||||||
| 159 | Calibration circuit | US12611598 | 2009-11-03 | US08364434B2 | 2013-01-29 | Hideyuki Yoko; Hiroki Fujisawa |
| To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer. | ||||||
| 160 | High frequency circuit having multi-chip module structure | US12786942 | 2010-05-25 | US08345434B2 | 2013-01-01 | Kazutaka Takagi |
| According to one embodiment, there is a high frequency circuit having a multi-chip module structure, including a semiconductor substrate set formed with discrete transistors connected in series, a first dielectric substrate set formed with capacitors, and a second dielectric substrate set formed with strip lines. | ||||||
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