| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 101 | Symmetric linear equalization circuit with increased gain | US14869346 | 2015-09-29 | US09419564B2 | 2016-08-16 | Armin Tajalli |
| Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals. | ||||||
| 102 | CIRCUITS AND METHODS FOR REDUCING SUPPLY SENSITIVITY IN A POWER AMPLIFIER | US14518967 | 2014-10-20 | US20160112018A1 | 2016-04-21 | Antonino Scuderi; Aristotele Hadjichristos |
| In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range. | ||||||
| 103 | Symmetric Linear Equalization Circuit with Increased Gain | US14869346 | 2015-09-29 | US20160072449A1 | 2016-03-10 | Armin Tajalli |
| Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals. | ||||||
| 104 | Method for digital programmable optimization of mixed-signal circuits | US12390792 | 2009-02-23 | US08742831B2 | 2014-06-03 | Paul S. Fechner |
| A method for digital programmable optimization of a mixed-signal circuit is provided. The method comprises dividing up one or more transistor devices of the mixed-signal circuit into one or more transistor segments, with each transistor segment including a body tie bias terminal. Each body tie bias terminal is coupled to at least one voltage bias, either by placing each body tie bias terminal in signal communication with one or more bias nodes in the mixed-signal circuit, or by placing each body tie bias terminal in signal communication with a non-precision bias voltage source. Each body tie terminal is also arranged to be in signal communication with a separate one of one or more digital programmable storage elements. | ||||||
| 105 | Adder, and power combiner, quadrature modulator, quadrature demodulator, power amplifier, transmitter and wireless communicator using same | US13127466 | 2009-11-05 | US08396435B2 | 2013-03-12 | Akira Nagayama; Yasuhiko Fukuoka |
| To provide an adder capable of obtaining an addition signal of a plurality of high frequency signals, and also a power combiner, a quadrature modulator, a quadrature demodulator, a power amplifier, a transmitter, and a wireless communicator, each of which uses the adder. Impedances (Zg, Zh) seen from a common output point (P3) of a plurality of first impedance circuits (110a, 110b) toward respective input terminals (102a, 102b) are set so that high frequency currents (Ig, Ih) are approximately zero. An impedance (Zs) seen from a first connection point (P1) toward the input terminals (102a, 102b) is set so that a high frequency current (Is) is approximately zero. An impedance (Zc) seen from the first connection point (P1) toward a circuit (150) is set so that a high frequency current (Ic) is approximately zero. An impedance (Zm) seen from a second connection point (P2) toward a power supply is set so that a high frequency current (Im) is approximately zero. | ||||||
| 106 | AMPLIFIER ARRANGEMENT | US13022113 | 2011-02-07 | US20120200359A1 | 2012-08-09 | Udo Karthaus; Lothar Schmidt |
| An amplifier arrangement with an amplifier arrangement input and an amplifier arrangement output is disclosed. The amplifier arrangement comprises a first transistor and a first ballast resistance, wherein the first ballast resistance connects a first transistor base of the first transistor to a common base terminal at least one second transistor and at least one second ballast resistance, wherein the at least one second ballast resistance connects a second transistor base of the at least second transistor to the common base terminal; and a feedback device comprising a feedback input terminal for sensing at least a base voltage of the first transistor and further comprising a feedback output terminal that is connected to the common base terminal. | ||||||
| 107 | Segmented Power Amplifier with Varying Segment Activation | US12789342 | 2010-05-27 | US20110291754A1 | 2011-12-01 | Vijay Kumar Reddy; Srikanth Krishnan; Brian P. Ginsburg; Srinath Mathur Ramaswamy; Chih-Ming Hung |
| Various apparatuses and methods for varying segment activation in a segmented power amplifier are disclosed herein. For example, some embodiments provide a power amplifier including an input, an output, a plurality of amplifier segments and a controller. The amplifier segments are connected in parallel between the input and the output and are adapted to be activated and inactivated. The power level at the output may be controlled by changing a number of the amplifier segments that are activated concurrently. The controller is connected to the amplifier segments and is adapted to vary which of the amplifier segments are activated to arrive at a selected number of activated amplifier segments. | ||||||
| 108 | Composite device having three output terminals | US12546112 | 2009-08-24 | US07939857B1 | 2011-05-10 | Michael A Wyatt |
| A composite device includes a depletion mode FET coupled to a bipolar transistor. The FET includes gate, drain and source terminals, and the bipolar transistor includes base, collector and emitter terminals. The collector terminal of the bipolar transistor and the source terminal of the depletion mode FET are directly connected to each other. Additionally, the emitter terminal of the bipolar transistor and the gate terminal of the depletion mode FET are directly connected to each other. The voltage between the collector and emitter terminals, VCE, is configured to bias the depletion mode FET. The VCE voltage has a value that is equal and opposite to a voltage VGS between the gate and source terminals of the depletion mode FET. | ||||||
| 109 | Radio frequency power amplifier | US12535309 | 2009-08-04 | US07834700B2 | 2010-11-16 | Masahiko Inamori; Kazuki Tateoka; Hirokazu Makihara; Shingo Matsuda; Junji Kaido |
| A radio frequency signal is input to the bases of transistors via respective capacitors, is amplified, and is output from the collectors of the transistors. The emitter of each transistor is grounded. A bias current input from a bias circuit is supplied to the bases of the transistors via respective resistors both during low-output operation and during high-output operation. The collectors of the transistors are connected via an impedance circuit to a bias voltage input terminal. Therefore, during high-output operation, a direct current offset voltage is generated by the impedance circuit based on a portion of a radio frequency signal output from the collectors, thereby further increasing the bias current. | ||||||
| 110 | AMPLIFIER CIRCUIT AND THE CONTROLLING METHOD THEREOF | US12481528 | 2009-06-09 | US20100244963A1 | 2010-09-30 | Yu Cheng HSU; De Cheng Chang |
| An amplifier circuit includes a first unit and a second unit. The first unit has a first amplifying unit, wherein the first amplifying unit provides a first main circuit unit and a first assistant circuit unit, and the first assistant circuit unit is configured for assisting the linearity of the first main circuit unit. The second unit includes a second amplifying unit, wherein the second amplifying unit has a second main circuit unit and a second assistant circuit unit, and the second assistant circuit unit is configured for assisting the linearity of the second main circuit unit. The first amplifying unit is configured for conducting in one half cycle of an input signal, and the second amplifying unit is configured for conducting in the other half cycle of the input signal. | ||||||
| 111 | Reconfigurable tunable RF power amplifier | US12126030 | 2008-05-23 | US07764125B2 | 2010-07-27 | Geoffrey C Dawe |
| A multi-band, multi-standard programmable power amplifier having tunable impedance matching input and output networks and programmable device characteristics. The impedance of either or both of the impedance matching input and output networks is tunable responsive to one or more control signals. In one example, the programmable power amplifier incorporates a feedback control loop and the control signal(s) are varied responsive to the feedback loop. | ||||||
| 112 | SEMICONDUCTOR DEVICE | US12715424 | 2010-03-02 | US20100156541A1 | 2010-06-24 | Akira Inoue; Seiki Goto; Kou Kanaya; Sinsuke Watanabe |
| A current limiting circuit is connected to the gate (input terminal) of an amplifying transistor. The current limiting circuit includes a protecting transistor, a first protecting resistor connecting the drain to the gate of the protecting transistor, and a second protecting resistor connecting the source to the gate of the protecting transistor. The current limiting circuit limits current, so that electric power larger than the maximum electric power allowable for the amplifying transistor does not pass. | ||||||
| 113 | CALIBRATION CIRCUIT | US12611598 | 2009-11-03 | US20100045359A1 | 2010-02-25 | Hideyuki Yoko; Hiroki Fujisawa |
| To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer. | ||||||
| 114 | Low noise amplifier | US12033044 | 2008-02-19 | US07663441B2 | 2010-02-16 | Byoung-Joong Kang |
| A low noise amplifier includes a main amplifier configured to amplify a first input signal to generate a first output signal and an auxiliary amplifier configured to amplify a second input signal to generate a second output signal. The auxiliary amplifier is coupled to the main amplifier for superposing the second output signal and the first output signal. The low noise amplifier also includes an adjusting unit configured to adjust a time constant for reducing a third order intermodulation distortion of the superposed signal in response to a control signal. The adjusting unit is configured to generate the second input signal based on the time constant and the first input signal. | ||||||
| 115 | Power amplifier | US11687770 | 2007-03-19 | US07619470B2 | 2009-11-17 | Kazuhide Abe; Tadahiro Sasaki; Kazuhiko Itaya; Hideyuki Funaki |
| A power amplifier includes: a plurality of field effect transistors connected in parallel and each having a first and second ends, the first end being connected to ground; an amplifying unit which includes at least one of an inductor, a capacitor and a band pass filter and has a third and fourth ends, the third end being connected to the second ends of the field effect transistors, and the fourth end outputting an amplified output signal; and an amplitude controller which sends control signals respectively to gates of the field effect transistors to turn on or off the field effect transistors based on an address signal for performing selection on the field effect transistors and a clock signal. Channel widths of the field effect transistors are different from each other. | ||||||
| 116 | Programmable radio transceiver | US11055589 | 2005-02-10 | US07580684B2 | 2009-08-25 | Russell J. Cyr; Geoffrey C. Dawe |
| A fully integrated, programmable mixed-signal radio transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the radio transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC includes a tunable resonant circuit that includes a transmission line having an inductance, a plurality of switchable capacitors configured to be switched into and out of the tunable resonant circuit in response to a first control signal, and at least one variable capacitor that can be varied in response to a second control signal, wherein a center resonant frequency of the resonant circuit is electronically tunable responsive to the first and second control signals that control a first capacitance value of the plurality of switchable capacitors and a second capacitance value of the at least one variable capacitor. | ||||||
| 117 | Amplifier coupling on a reduced area | US11576223 | 2004-09-30 | US07535304B2 | 2009-05-19 | Ulf Joakim Nilsson |
| The invention discloses an amplifier (200, 400, 500) coupling comprising a first (230), a second (240), a third (250) and a fourth (260) transistor, additionally comprising a signal input port (220) and a signal output port (210, 410). The input port of the amplifier is connected to the first, second, third and fourth transistors such that an input signal to the amplifier is input to the first and the fourth transistor in parallel, and to the second and third transistors in parallel, with the outputs from the first and second transistors being connected in series to each other, and the outputs from the fourth and third transistors being connected in series with each other, said outputs being connected in parallel to each to the one output port of the amplifier. | ||||||
| 118 | Voltage buffer for capacitive loads | US11620001 | 2007-01-04 | US07471139B2 | 2008-12-30 | Shahzad Khalid |
| A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is connected to have the same control gate level as the transistor in the feedback loop and provide an output voltage based on the reference input voltage. The output voltage is dependent upon the input voltage, but the load is removed from the feedback loop. By removing the load from the feedback loop, the loop is stabilized with only a very small or no compensating capacitor, allowing the quiescent current of the buffer to be reduced and the settling time to be improved. One preferred use of the present invention is to drive the data storage elements of a non-volatile memory. | ||||||
| 119 | Integrated Circuit Amplifiers Having Switch Circuits Therein that Provide Reduced 1/f Noise | US12203260 | 2008-09-03 | US20080315950A1 | 2008-12-25 | Jeongwook Koh; Chun-Deok Suh; Eun-Chul Park |
| Integrated circuit devices include a pair of field effect transistors having shared source terminals, shared drain terminals and shared gate terminals, which may be treated herein as being electrically coupled in parallel. A switch circuit is also provided, which is configured to drive a body terminal of a first one of the pair of field effect transistors with an alternating sequence of first and second unequal body voltages. This alternating sequence is synchronized with a first clock signal. The switch circuit is also configured to drive a body terminal of a second one of the pair of field effect transistors with an alternating sequence of third and fourth unequal body voltages, which is synchronized with a second clock signal. The first and third body voltages may have equivalent magnitudes and the second and fourth body voltages may have equivalent magnitudes. The first and second clock signals may have 50% duty cycles and may be 180 degrees out-of-phase relative to each other. | ||||||
| 120 | RECONFIGURABLE TUNABLE RF POWER AMPLIFIER | US12126030 | 2008-05-23 | US20080290947A1 | 2008-11-27 | Geoffrey C. Dawe |
| A multi-band, multi-standard programmable power amplifier having tunable impedance matching input and output networks and programmable device characteristics. The impedance of either or both of the impedance matching input and output networks is tunable responsive to one or more control signals. In one example, the programmable power amplifier incorporates a feedback control loop and the control signal(s) are varied responsive to the feedback loop. | ||||||
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