| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 增益特性补偿电路 | CN98124877.2 | 1998-11-27 | CN1088940C | 2002-08-07 | 角田雄二; 深泽善亮; 田口雄一 |
| 本发明可用于补偿由环境温度变化引起的增益斜率的增益特性的波动。无须增加电路规模，也无须提高成本。作为阻值对温度敏感的部件的热敏电阻，其有效阻值随环境温度变化而呈负温度特性。本发明采用该类热敏电阻作为FET(场效应管)的栅极电阻。这种电路的功能在于使增益斜率的增益特性相对于环境温度的波动被Q值相对于环境温度的波动所抵消。因此，可以补偿随环境温度而变的增益斜率特性的波动。 | ||||||
| 2 | 增益特性补偿电路 | CN98124877.2 | 1998-11-27 | CN1219022A | 1999-06-09 | 角田雄二; 深泽善亮; 田口雄一 |
| 本发明可用于补偿由环境温度变化引起的增益叙率的增益特性的波动。无须增加电路规模,也无须提高成本。作为阻值对温度敏感的部件的热敏电阻,其有效阻值随环境温度变化而呈负温度特性。本发明采用该类热敏电阻作为FET(场效应管)的栅极电阻。这种电路的功能在于使增益斜率的增益特性相对于环境温度的波动被Q值相对于环境温度的波动所抵消。因此,可以补偿随环境温度而变的增益斜率特性的波动。 | ||||||
| 3 | Single-ended input to differential-ended output low noise amplifier | JP2007017554 | 2007-01-29 | JP2007235938A | 2007-09-13 | KAO NIEN-AN; CHANG KWO-WEI |
| PROBLEM TO BE SOLVED: To provide a single-ended input/differential-ended output amplifier including an amplifier and a single-ended input/differential-ended output conversion circuit. SOLUTION: The present invention includes a single-ended input/differential-ended output conversion circuit, for converting an amplified signal to a differential signal pair, comprising a first transistor having a first gate coupled to a single-ended amplified signal of an amplifier, a first first terminal coupled to a second output 409 and a first second terminal coupled to a first node B; a second capacitor 406 having a second gate, a second first terminal coupled to a third output 409' and a second second terminal coupled to the second node B; a second capacitor 406 coupled between the second output and the second gate; a first resistor 403 coupled between the second output and a voltage source; a second resistor 404 coupled between the third output and the voltage source; and a current source 405 coupled between a first node and a ground. COPYRIGHT: (C)2007,JPO&INPIT | ||||||
| 4 | デジタル可変容量回路、共振回路、増幅回路、及び送信機 | JP2015166736 | 2015-08-26 | JP2017046155A | 2017-03-02 | 溝神 正和 |
| 【課題】高性能のデジタル可変容量回路、共振回路、増幅回路、及び送信機を提供すること。 【解決手段】 本実施の形態にかかるデジタル可変容量回路50は、2つの出力端子OUTP,OUTNの間に並列接続された複数のユニット容量セル51−0〜51−nを有するデジタル可変容量回路であって、ユニット容量セル51が、一端が一方の出力端子OUTPと接続された第1の容量Cu1と、2つの出力端子の間において、第1の容量Cu1と直列接続された第2の容量Cu2と、第2の容量Cu2と並列接続され、デジタル制御信号に応じて制御されるNMOSトランジスタM1と、を備えるものである。 【選択図】図13 |
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| 5 | プログラマブル低雑音増幅装置 | JP2009500202 | 2008-02-20 | JPWO2008102788A1 | 2010-05-27 | 米谷 昭彦; 昭彦 米谷 |
| 小型化が進むチューナに用いる低雑音増幅器は省電力化と低雑音化という性能を求められている。低雑音化を図るために、入信した信号のレベルに基づいて利得を変化させるようにすることが望ましい。また、省電力化や低電圧化を図るためにはトランジスタの縦積み段数を減らすことが必要である。そこで、ゲート接地されたトランジスタとカスコード接続された1対のトランジスタで構成される固定増幅器と、利得の絶対値が同じで固定増幅器の利得を加算する増幅器と減算する増幅器を複数個備え、スイッチでこれらの増幅器を選択することで全体の利得を可変にするとともに、トランジスタの縦積み段数を2段にしたプログラマブル利得可変低雑音増幅装置を提供する。 | ||||||
| 6 | LOW NOISE AMPLIFIER METHOD AND APPARATUS | EP14791244 | 2014-05-02 | EP2992603A4 | 2017-02-15 | SHAW ROBERT DOUGLAS |
| 7 | LOGARITHMIC DETECTOR AMPLIFIER SYSTEM FOR USE AS HIGH SENSITIVITY SELECTIVE RECEIVER WITHOUT FREQUENCY CONVERSION | EP14844032.4 | 2014-03-14 | EP3044723A1 | 2016-07-20 | RADA, Patrick, Antoine; BROWN, Forrest, James; DUPUY, Alexandre |
| A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency. | ||||||
| 8 | LOW NOISE AMPLIFIER METHOD AND APPARATUS | EP14791244.8 | 2014-05-02 | EP2992603A1 | 2016-03-09 | SHAW, Robert Douglas |
| A low noise amplifier circuit including: at least a first input and first output; at least a first stage of transistor amplification having a transistor input terminal; the circuit further comprising: an input driving circuit interconnecting the first input to the transistor input terminal, the input driving circuit including a parallel resonant circuit interconnected between the transistor input terminal and ground and a series resonant circuit interconnected between the input terminal and the transistor input terminal, the input driving circuit functioning as an input matching network for the circuit in conjunction with an input bias and decoupling network. | ||||||
| 9 | Compensatory circuit with gain character | EP98122467.8 | 1998-11-26 | EP0920124A2 | 1999-06-02 | Kakuta, Yuji; Fukasawa, Yoshiaki; Taguchi, Yuichi c/o NEC Engineering, Ltd. |
Compensating for fluctuations in the gain characteristic of the gain slope in the event of changes in ambient temperature without increasing circuit scale or adding to costs. A thermistor, which is a thermally sensitive resistance element in which resistance changes with a negative temperature characteristic according to the ambient temperature, is employed as the gate resistance of an FET, and the circuit functions such that fluctuations in the gain characteristic of the gain slope with respect to ambient temperature are canceled out by fluctuations in the value of Q with respect to the ambient temperature, thereby compensating for fluctuations in the gain slope characteristic in the event of changes in the ambient temperature. |
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| 10 | POWER AMPLIFIER | US15800779 | 2017-11-01 | US20180287561A1 | 2018-10-04 | Hyeon Seok HWANG; Jong Soo LEE; Seung Chul PYO |
| A power amplifier includes an amplifying circuit configured to amplify an input signal and comprising transistors, which may be disposed in parallel with one another and divided into a first group of transistors and a second group of transistors. The power amplifier also includes a bias circuit configured to supply bias power to one of the transistors of the first group and the transistors of the second group. | ||||||
| 11 | Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion | US15916864 | 2018-03-09 | US20180205350A1 | 2018-07-19 | Patrick Antoine Rada; Forrest James Brown; Alexandre Dupuy |
| An amplifying system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The amplifying system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency. | ||||||
| 12 | Digital variable capacitance circuit, resonant circuit, amplification circuit, and transmitter | US15187608 | 2016-06-20 | US09843344B2 | 2017-12-12 | Masakazu Mizokami |
| The present invention aims to provide a digital variable capacitance circuit, a resonant circuit, an amplification circuit, and a transmitter having a high performance. A digital variable capacitance circuit 50 according to this embodiment is a digital variable capacitance circuit including a plurality of unit capacity cells 51-0 to 51-n connected in parallel between two output terminals OUTP and OUTN, in which the unit capacity cell 51 comprises: a first capacitor Cu1 having one end connected to one output terminal OUTP; a second capacitor Cu2 that is connected in series with the first capacitor Cu1 between the two output terminals; and an NMOS transistor M1 that is connected in parallel with the second capacitor Cu2 and is controlled in accordance with a digital control signal. | ||||||
| 13 | High-linearity low noise amplifier | US12422430 | 2009-04-13 | US08018288B2 | 2011-09-13 | Jon S. Duster; Stewart S. Taylor |
| Embodiments of a high-linearity low-noise amplifier (LNA) are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier. The cascode amplifier may include integrated notch filters to attenuate undesired signals. The cascode amplifier may operate from a large power supply when blockers are present to avoid voltage swing compression at its output. The cascode amplifier may be biased and designed to operate in a class AB mode to produce linear output current to avoid current compression or excessive current expansion. | ||||||
| 14 | WIDEBAND LOW NOISE AMPLIFIERS | US12030808 | 2008-02-13 | US20090121791A1 | 2009-05-14 | Shey-Shi LU; Hsien-Ku CHEN |
| A wideband low noise amplifier. The wideband low noise amplifier comprises an amplifier, an output device, and an inductor. The amplifier amplifies an input signal received from an input node, and outputs the amplified signal to an output node. The output device is coupled to a first voltage and the output node. The peaking inductor is coupled between the amplifier and the output device. | ||||||
| 15 | CONFIGURABLE CIRCUITS USING PHASE CHANGE SWITCHES | US11461564 | 2006-08-01 | US20080029753A1 | 2008-02-07 | Yang Xu; Lawrence Pileggi; Mehdi Asheghi |
| Configurable circuits using phase change switches are described. The switches use phase change or phase transition material to create configurable connections between devices and/or interconnecting layers of an integrated circuit in order to change the behavior of the circuit after manufacturing. In at least some embodiments, the phase of the material can be a crystalline phase or an amorphous phase. A phase change can be caused by heating the material, such as with an ohmic heater fabricated on the IC. As one example, germanium-antimony-tellurium (GeSbTe) can be used for the phase change material. The switches can be used to create configurable circuits such as low noise amplifiers and mixers, which can in turn be used to create configurable receivers or other analog circuits. | ||||||
| 16 | Semiconductor circuit compensating for changes in gain slope of the circuit's gain-frequency characteristic caused by ambient temperature changes | US195621 | 1998-11-19 | US6147557A | 2000-11-14 | Yuji Kakuta; Yoshiaki Fukasawa; Yuichi Taguchi |
| Compensating for fluctuations in the gain characteristic of the gain slope in the event of changes in ambient temperature without increasing circuit scale or adding to costs. A thermistor, which is a thermally sensitive resistance element in which resistance changes with a negative temperature characteristic according to the ambient temperature, is employed as the gate resistance of an FET, and the circuit functions such that fluctuations in the gain characteristic of the gain slope with respect to ambient temperature are canceled out by fluctuations in the value of Q with respect to the ambient temperature, thereby compensating for fluctuations in the gain slope characteristic in the event of changes in the ambient temperature. | ||||||
| 17 | 周波数変換することなく高感度選択的受信機として使用する対数検出増幅器システム | JP2016541953 | 2014-03-14 | JP2016533688A | 2016-10-27 | パトリック・アントワーヌ・ラダ; フォレスト・ジェイムズ・ブラウン; アレクサンドル・デュピュイ |
| 対数検出増幅(LDA)システムは、通信装置の受信チェーンにおいて低雑音増幅器のための高感度受信ブースタ又はその置き換えを使用するために提供される。LDAシステムは、第1の周波数を有する入力信号を受信し、入力信号に基づいて発振を発生するように構成された増幅回路と、増幅回路に接続され、発振を周期的にクランプして再起動するように所定のしきい値に基づいて発振を停止させることで発振及び入力信号により変調されたパルス列を発生するサンプリング回路と、増幅回路と接続され動作周波数を確立して第2の周波数を有する出力信号を発生するように構成された1つ又は複数の共振回路とを備え、第2の周波数は第1の周波数と実質的に同じである。 | ||||||
| 18 | Transistor circuit | JP2004293006 | 2004-10-05 | JP4756843B2 | 2011-08-24 | 克彦 川島; 慎吾 松田; 弘和 牧原; 一樹 立岡 |
| 19 | Transistor circuit | JP2004293006 | 2004-10-05 | JP2006108385A | 2006-04-20 | MAKIHARA HIROKAZU; TATSUOKA KAZUKI; KAWASHIMA KATSUHIKO; MATSUDA SHINGO |
| PROBLEM TO BE SOLVED: To provide a transistor circuit capable of preventing the thermal runaway of a transistor and capable of largely reducing the power gains of unwanted harmonic components and an out-of-band signal components, while inhibiting lowering of the power gain of a desired frequency component by a base ballast resistor. SOLUTION: The transistor circuit 1 is composed of a plurality of transistor cells 10, constituted of the transistors 11, the base ballast resistors 12, capacitors 13, and inductors 14. Collectors and emitters for the transistors 11 are commonly connected at a collector terminal 1c and an emitter terminal 1e for the transistor circuit 1, respectively. In the base ballast resistors 12, one end of the resistor 11 connected to a base for the transistor 11 and the other end to a base terminal 1b for the transistor circuit 1. The capacitors 13 and the inductors 14 are connected in series and form series resonance circuits 15, and are connected among the bases for the transistors 11 and the base terminals 1b for the transistor circuit 1, in parallel with the base ballast resistors 12. COPYRIGHT: (C)2006,JPO&NCIPI | ||||||
| 20 | 주파수 변환 없이 고감도 선택적 수신기로서 사용되기 위한 대수 검출 증폭기 시스템 | KR1020187021599 | 2014-03-14 | KR1020180088921A | 2018-08-07 | |
| 고감도수신부스터및 통신장치의수신체인내 저잡음증폭기에대한대체품으로서사용되기위한대수검출기증폭(LDA) 시스템이제공된다. 상기 LDA 시스템은제1 주파수를갖는입력신호를수신하고입력신호를기초로발진을생성하도록구성된증폭회로, 상기증폭회로에연결되고지정임계치를기초로상기발진을종료하여상기발진을주기적으로고정및 재시작하여발진및 입력신호에의해변조되는일련의펄스를생성하도록구성된샘플링회로, 및증폭회로와연결되며동작의주파수를확립하며, 제2 주파수를갖는출력신호를생성하도록구성된하나이상의공진회로를포함하며, 상기제2 주파수는제1 주파수와실질적으로동일하다. | ||||||
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