| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 放大器输入级和放大器 | CN201510239369.2 | 2015-05-08 | CN105099379A | 2015-11-25 | R·S·毛瑞诺 |
| 本发明涉及放大器输入级和放大器。放大器输入级包括第一和第二P型晶体管；第一和第二n型晶体管，其中第一和第二n型晶体管的源极连接到第二节点，所述第一n型晶体管的漏极被连接到放大器输入级的第三输出，所述第二n型晶体管的漏极被连接到放大器输入级的第四输出，所述第一n型晶体管的栅极被配置为接收所述输入级差分输入信号的第一信号，以及所述第二n型晶体管的栅极被配置成接收所述输入级差分输入信号的第二信号；第一电路，被布置为提供第一偏置电流到所述第一节点的一第一部分；和第二电路，被布置为从第二节点的第二部分引流所述第一偏置电流；其中第一和第二部分由放大器输入信号的第一信号进行确定。 | ||||||
| 2 | 具有DC-DC转换器的GSM-GPRS-EDGE功率放大器中的杂散消除 | CN201380068981.7 | 2013-10-30 | CN104904119A | 2015-09-09 | 阿列克桑德尔·戈尔巴乔夫 |
| 公开了一种用于GSM/GPRS/EDGE收发器的具有杂散消除的射频(RF)功率放大器电路。具有包括RF输入端、RF输出端和电压电源输入端的功率放大器。此外，具有包括与电池连接的输入端、与生成DC电源电压信号的功率放大器的电压电源输入端连接的输出端在内的可调DC-DC转换器。杂散补偿器响应于DC电源电压信号中的杂散而生成差错控制信号。该差错控制信号被施加到功率放大器的RF输入端。 | ||||||
| 3 | 电流控制装置与信号转换装置 | CN201410768286.8 | 2014-12-12 | CN104716916A | 2015-06-17 | 吴旻桦; 楼志宏; 黄彦筌; 王麒云 |
| 一种电流控制装置与信号转换装置，该电流控制装置包含：第一电阻电路，用以根据第一控制信号来选择性地自第一输入端传导第一电流至第一输出端；以及第二电阻电路，用以根据第二控制信号来选择性地自该第一输入端传导一第二电流至第二输出端；其中当第一电阻电路自第一输入端传导第一电流至第一输出端且第二电阻电路未自该第一输入端传导第二电流至第二输出端时，第一输入端具有第一输入阻抗；当第一电阻电路并未自第一输入端传导第一电流至第一输出端且第二电阻电路自第一输入端传导第二电流至第二输出端时，第一输入端具有一第二输入阻抗，第一输入阻抗与第二输入阻抗相同。本发明可在提供至少两个不同频率位移以及相位位移工作周期的架构的同时，减少所需的硬件部件的数量。 | ||||||
| 4 | CIRCUITS AND METHODS FOR REDUCING SUPPLY SENSITIVITY IN A POWER AMPLIFIER | EP15784905.0 | 2015-10-13 | EP3210298A1 | 2017-08-30 | SCUDERI, Antonino; HADJICHRISTOS, Aristotele |
| In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range. | ||||||
| 5 | AMPLIFIER SYSTEM, CONTROLLER OF MAIN AMPLIFIER AND ASSOCIATED CONTROL METHOD | EP16185674.5 | 2016-08-25 | EP3168986A1 | 2017-05-17 | LIN, Lai-Ching; TSAI, Ming-Da |
The present invention provides a control circuit (1 20) to stabilize an output power of a power amplifier (110). The control circuit (120) comprises a voltage clamping loop (1 30), a current clamping loop (140) and a loop (1 50) for reducing power variation under VSWR, where the voltage clamping loop (1 30) is used to clamp an output voltage of the power amplifier (110) within a defined voltage range, the current clamping loop (140) is used to clamp a current of the power amplifier (110) within a defined current range, and the loop (1 50) for reducing power variation under VSWR is implemented by an impedance detector (1 50) to compensate the output power under VSWR variation.
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| 6 | 増幅回路 | JP2017090051 | 2017-04-28 | JP2018191068A | 2018-11-29 | 杉本 良之 |
| 【課題】低消費電力化が可能な増幅回路を実現する。 【解決手段】帰還用アンプ30は、一方の入力信号が入力される入力端子INPと、他方の入力信号が入力される入力端子INNと、入力端子INP,INN側にアノードが接続されたダイオード対53と、ダイオード対53のカソードにそれぞれ接続され、ダイオード対53のそれぞれに電流を供給するバイアス電流源54と、ダイオード対53のカソードに接続され、ダイオード対53のカソードに生じた信号の差信号を増幅するCMOS構成のオペアンプ56と、オペアンプ56の入出力間に接続された容量素子57と、オペアンプ56と入力端子INP,INNとの間に設けられ、入力信号を増幅するバイポーラトランジスタ対63a,63bを含む差動アンプ52とを備え、バイアス電流源54は、カレントミラー回路部55を含む。 【選択図】図2 |
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| 7 | 半導体装置及びそれを備えた電子制御システム | JP2016004864 | 2016-01-14 | JP2017125756A | 2017-07-20 | 黒岡 一晃; 森本 康夫; 船戸 是宏 |
| 【課題】コンバータを形成するチップ上に設けられた既存の外部端子の電位を用いて、レゾルバの短絡故障の有無を正確に検知することが可能な半導体装置を提供すること。 【解決手段】一実施の形態によれば、半導体装置は、レゾルバ11の検知結果に応じた一対の電圧信号の一方及び他方がそれぞれ入力抵抗R1,R3を介して供給される外部端子S1,S3と、外部端子S1,S3に供給された一対の電圧信号の電位差を増幅するオペアンプAP11と、オペアンプAP11の出力端子及び一方の入力端子間に設けられた帰還抵抗R13と、オペアンプAP11の2つの入力端子と外部端子S1,S3と、の間にそれぞれ設けられたスイッチSW1,SW3と、スイッチSW1,SW3がオフしたときの外部端子S1,S3のそれぞれの電圧レベルに基づいて、レゾルバ11において短絡故障が発生したか否かを検知する、短絡故障検知回路102と、を備える。 【選択図】図1 |
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| 8 | Current controlling device and signal converting apparatus applying the current controlling device | EP14197124.2 | 2014-12-10 | EP2890006B1 | 2018-07-18 | Wu, Min-Hua; Lou, Chih-Hong; Huang, Yen-Chuan; Wang, Chi-Yun |
| A current controlling device (100) includes: a first resistive circuit (102) arranged to selectively conduct a first current (I1) to a first output terminal (No1) from a first input terminal (Ni1); and a second resistive circuit (104) arranged to selectively conduct a second current (12) to a second output terminal (No2) from the first input terminal (Ni1); wherein when the first resistive circuit (102) conducts the first current (I1) to the first output terminal (No1) and when the second resistive circuit (104) does not conduct the second current (I2) to the second output terminal (No2), the first input terminal (Ni1) has a first input impedance; when the first resistive circuit (102) does not conduct the first current (I1) to the first output terminal (No2) and when the second resistive circuit (104) conducts the second current (I2) to the second output terminal (No2), the first input terminal (Ni1) has a second input impedance substantially equal to the first input impedance. | ||||||
| 9 | Current controlling device and signal converting apparatus applying the current controlling device | EP14197124.2 | 2014-12-10 | EP2890006A1 | 2015-07-01 | Wu, Min-Hua; Lou, Chih-Hong; Huang, Yen-Chuan; Wang, Chi-Yun |
A current controlling device (100) includes: a first resistive circuit (102) arranged to selectively conduct a first current (I1) to a first output terminal (No1) from a first input terminal (Ni1); and a second resistive circuit (104) arranged to selectively conduct a second current (12) to a second output terminal (No2) from the first input terminal (Ni1); wherein when the first resistive circuit (102) conducts the first current (I1) to the first output terminal (No1) and when the second resistive circuit (104) does not conduct the second current (I2) to the second output terminal (No2), the first input terminal (Ni1) has a first input impedance; when the first resistive circuit (102) does not conduct the first current (I1) to the first output terminal (No2) and when the second resistive circuit (104) conducts the second current (I2) to the second output terminal (No2), the first input terminal (Ni1) has a second input impedance substantially equal to the first input impedance.
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| 10 | Amplifier | EP09252522.9 | 2009-10-30 | EP2317646A1 | 2011-05-04 | Teng, Robert Hwat Hian |
An amplifier 100 has an input 108 for receiving a signal to be amplified and an output 110 for outputting an amplified signal. The amplifier 100 comprises a main amplification stage 102, an auxiliary amplification stage 104 and a controller 106. The main amplification stage 102 comprises a main amplification circuit 200 and the auxiliary amplification stage 104 comprises an auxiliary amplification circuit 202. Each of the main amplification circuit 200 and the auxiliary amplification circuit 202 comprises a p-channel metal oxide semiconductor (PMOS) transistor T1, T3 and an n-channel metal oxide semiconductor (NMOS) transistor T2, T4. The PMOS and NMOS transistors T3, T4 of the auxiliary amplification circuit 202 are either identical to the PMOS and NMOS transistors T1, T2 of the main amplification circuit 200 or are scaled down copies of the PMOS and NMOS transistors T1, T2 of the main amplification circuit 200. The auxiliary amplification circuit 202 amplifies the input signal to generate a control signal and the controller 106 controls a function of the amplifier 100 based on the control signal.
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| 11 | SEMICONDUCTOR DEVICE AND ELECTRONIC CONTROL SYSTEM INCLUDING THE SAME | US15987572 | 2018-05-23 | US20180267092A1 | 2018-09-20 | Kazuaki KUROOKA; Yasuo MORIMOTO; Yoshihiro FUNATO |
| According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state. | ||||||
| 12 | ACTIVE RC FILTERS | US15536504 | 2015-12-14 | US20170346456A1 | 2017-11-30 | Phil Corbishley |
| An operational amplifier comprises: a first amplifier stage 4 comprising a first differential pair of transistors 8, 10 arranged to receive and amplify a differential input signal 18, 20 thereby providing a first differential output signal 22, 24; and a second amplifier stage 6 comprising a second differential pair of transistors 26, 28 arranged to receive and amplify the first differential output signal 22, 24 thereby providing a second differential output signal 38, 40. | ||||||
| 13 | Feedback type voltage regulator | US14846816 | 2015-09-06 | US09753475B2 | 2017-09-05 | Yu-Po Lin; Kea-Tiong Tang |
| The present invention discloses a feedback type voltage regulator, including a voltage reference circuit for providing a reference voltage, distributed series feedback amplifiers electrically coupled to the voltage reference circuit and a power transistor which gate is electrically connected to the distributed series feedback amplifiers. The distributed series feedback amplifiers comprises three set of amplifiers serially connected with each other, wherein the relation of the gain of the first amplifier (A1), the second amplifier (A2), and the third amplifier (A3) is A1>A2>A3, wherein the relation of the bandwidth of the first amplifier (B1), the second amplifier (B2), and the third amplifier (B3) is B1 | ||||||
| 14 | SEMICONDUCTOR DEVICE AND ELECTRONIC CONTROL SYSTEM INCLUDING THE SAME | US15402660 | 2017-01-10 | US20170205458A1 | 2017-07-20 | Kazuaki KUROOKA; Yasuo MORIMOTO; Yoshihiro FUNATO |
| According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state. | ||||||
| 15 | AMPLIFIER SYSTEM, CONTROLLER OF MAIN AMPLIFIER AND ASSOCIATED CONTROL METHOD | US15241035 | 2016-08-18 | US20170141748A1 | 2017-05-18 | Lai-Ching Lin; Ming-Da Tsai |
| The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation. | ||||||
| 16 | Accurate sample latch offset compensation scheme | US14818091 | 2015-08-04 | US09614502B2 | 2017-04-04 | Minhan Chen; Kenneth Luis Arcudia |
| A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors. | ||||||
| 17 | ACCURATE SAMPLE LATCH OFFSET COMPENSATION SCHEME | US14818091 | 2015-08-04 | US20170040983A1 | 2017-02-09 | Minhan Chen; Kenneth Luis Arcudia |
| A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors. | ||||||
| 18 | Operational amplifier circuit and method for enhancing driving capacity thereof | US14741469 | 2015-06-17 | US09467108B2 | 2016-10-11 | Chieh-An Lin; Chun-Yung Cho; Ju-Lin Huang |
| An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided. | ||||||
| 19 | OPERATIONAL AMPLIFIER CIRCUIT AND METHOD FOR ENHANCING DRIVING CAPACITY THEREOF | US14741469 | 2015-06-17 | US20150280664A1 | 2015-10-01 | Chieh-An Lin; Chun-Yung Cho; Ju-Lin Huang |
| An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided. | ||||||
| 20 | Operational amplifier circuit and method for enhancing driving capacity thereof | US14016136 | 2013-09-02 | US09106189B2 | 2015-08-11 | Chieh-An Lin; Chun-Yung Cho; Ju-Lin Huang |
| An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided. | ||||||
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