序号 | 专利名 | 申请号 | 申请日 | 公开(公告)号 | 公开(公告)日 | 发明人 |
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41 | Low distortion variable gain amplifier (VGA) | US13291782 | 2011-11-08 | US08698555B2 | 2014-04-15 | Steve Fang; Qiang Tang; Myung Jae Yoo |
In one embodiment, an apparatus an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier, the input node receiving the asymmetric signal. A second resistance is coupled to the input node of the amplifier. The second resistance includes a linear resistor. A third resistance is coupled to the second resistance. The third resistance is varied to adjust an amount of asymmetric correction provided by the amplifier to correct the asymmetric signal at the output node. The amount of asymmetric correction is a function of the first resistance and a combination of the second resistance and the third resistance. | ||||||
42 | 光電変換装置 | JP2017028419 | 2017-02-17 | JP2018133784A | 2018-08-23 | 柴田 政範; 塩道 寛貴 |
【課題】光電変換装置において、電源電圧の変動に対して有利な技術を提供する。 【解決手段】受光素子111を含む受光素子部101と、受光素子部から出力される信号を電圧に変換するための第1および第2のトランスインピーダンスアンプ103,104と、第1および第2のトランスインピーダンスアンプの出力を差動増幅する差動演算部105と、切替部102と、を含む光電変換装置100であって、切替部は、受光素子部と第1および第2のトランスインピーダンスアンプとの接続を切り替える出力切替部112a、112bと、第1および第2のトランスインピーダンスアンプの入力側の容量値を調整するために、第1および第2のトランスインピーダンスアンプのそれぞれ入力端子に接続された容量調整部120と、を含む。 【選択図】図1 |
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43 | 電圧検出装置、それを備えた温度検出装置、電圧検出方法、及び、それを備えた温度検出方法 | JP2016242904 | 2016-12-15 | JP2018096888A | 2018-06-21 | 帶刀 政文 |
【課題】広範囲の電圧を精度良く検出することが可能な電圧検出装置、それを備えた温度検出装置、電圧検出方法、及び、それを備えた温度検出方法を提供すること。 【解決手段】一実施の形態によれば、電圧検出装置は、検出電圧Vi1が反転入力端子に入力され、外部出力端子OUTの電圧Voutが非反転入力端子に入力される、オペアンプA1と、外部出力端子OUTと基準電圧端子GNDとの間に設けられ、オペアンプA1の出力電圧Vo1がゲートに印加されたトランジスタMN1と、検出電圧Vi2が反転入力端子に入力され、外部出力端子OUTの電圧Voutが非反転入力端子に入力される、オペアンプA2と、外部出力端子OUTと基準電圧端子GNDとの間に設けられ、オペアンプA2の出力電圧Vo2がゲートに印加されたトランジスタMN2と、を備える。 【選択図】図1 |
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44 | 能動RCフィルタ | JP2017531913 | 2015-12-14 | JP2017538364A | 2017-12-21 | コルビシュレイ、フィル |
演算増幅器は、差動入力信号18、20を受信して増幅することによって第一差動出力信号22、24を提供するように設けられた第一差動対トランジスタ8、10を備えた第一増幅段4と、第一差動出力信号22、24を受信して増幅することによって第二差動出力信号38、40を提供するように設けられた第二差動対トランジスタ26、28を備えた第二増幅段6と、を備える。【選択図】図1 | ||||||
45 | 電力増幅器において供給感度を低減するための回路および方法 | JP2017521136 | 2015-10-13 | JP2017531407A | 2017-10-19 | スクデリ、アントニーノ; ハドジクリストス、アリストテール |
一実施形態において、本開示は、入力信号を受けるための入力と、出力ノードに結合された出力とを有する第1の電力増幅器のステージを備える回路を含み、第1の電力増幅器のステージは、時変電源電圧を受ける。回路は、入力信号を受けるための入力と、出力ノードに結合された出力とを有する、第1の電力増幅器のステージと並列に構成される第2の電力増幅器のステージをさらに含み、第2の電力増幅器のステージは、時変電源電圧を受ける。第1の電力増幅器のステージの第1の利得は、電源電圧が第1の低電圧範囲にあるとき減少し、および第2の電力増幅器のステージの第2の利得は、第1の低電圧範囲における第1の電力増幅器のステージの減少する利得を補う。 | ||||||
46 | Low distortion variable gain amplifier (vga) | JP2011247734 | 2011-11-11 | JP2012114903A | 2012-06-14 | STEVE VAN; ZHANG TANG; YOO MYUNG JAE |
PROBLEM TO BE SOLVED: To correct the asymmetry of an asymmetric signal.SOLUTION: A first resistance is coupled between an input node and an output node of an amplifier, the input node receiving an asymmetric signal. A second resistance is coupled to the input node of the amplifier. The second resistance includes a linear resistor. A third resistance is coupled to the second resistance. The third resistance is varied to adjust an amount of asymmetric correction provided by the amplifier to correct the asymmetric signal at the output node. The amount of asymmetric correction is a function of the first resistance and a combination of the second resistance and the third resistance. | ||||||
47 | Output buffer amplifier | JP11978292 | 1992-04-13 | JP3347359B2 | 2002-11-20 | ミストルベルガー フリツツ; コツホ ルードルフ |
48 | ACTIVE RC FILTERS | EP15813516.0 | 2015-12-14 | EP3235127A1 | 2017-10-25 | CORBISHLEY, Phil |
An operational amplifier comprising two cascaded differential stages and suitable for an RC filter An operational amplifier with a differential input and a differential output comprises two cascaded differential stages 4 and 6 of relatively low gain, a dominant pole compensation capacitor being placed between the output nodes of the second stage 6. The propagation delay and power consumption may be low. The output common-mode voltage of the first or second stage may be controlled by use of a local replica circuit adjusting the current sources 12, 30. The amplifier may be used in a leapfrog active RC filter (figure 2). | ||||||
49 | SPUR CANCELLATION IN GSM-GPRS-EDGE POWER AMPLIFIERS WITH DC-DC CONVERTERS | EP13850773 | 2013-10-30 | EP2915249A4 | 2016-07-20 | GORBACHOV OLEKSANDR |
50 | SPUR CANCELLATION IN GSM-GPRS-EDGE POWER AMPLIFIERS WITH DC-DC CONVERTERS | EP13850773.6 | 2013-10-30 | EP2915249A2 | 2015-09-09 | GORBACHOV, Oleksandr |
A radio frequency (RF) power amplifier circuit with spur cancellation for GSM/GPRS/EDGE transceivers is disclosed. There is a power amplifier with an RF input, an RF output, and a voltage supply input. Additionally, there is an adjustable DC-DC converter with an input connected to a battery, an output connected to the voltage supply input of the power amplifier with a DC supply voltage signal generated thereby. A spur compensator generates an error control signal responsive to spurs in the DC supply voltage signal. The error control signal is applied to the RF input of the power amplifier. | ||||||
51 | Ausgangspufferverstärker mit grossem Signalhub | EP91106068.9 | 1991-04-16 | EP0509113B1 | 1998-10-07 | Koch, Rudolf, Dr.; Mistlberger, Fritz |
52 | Ausgangspufferverstärker mit grossem Signalhub | EP91106068.9 | 1991-04-16 | EP0509113A1 | 1992-10-21 | Koch, Rudolf, Dr.; Mistlberger, Fritz |
Ausgangspufferverstärker mit einer Endstufe (1, 2, 3, 4, 7, 8) für kleine Ausgangsleistungen und einer Endstufe (9, 10, 13, 14, 15, 16) für große Ausgangsleistungen, deren Ausgänge miteinander verbunden sind, und mit einer Regelstufe (12), die der Endstufe (1, 2, 3, 4, 7, 8) für kleine Ausgangsleistungen vorgeschaltet ist und deren einer Eingang durch ein einem Eingangssignal der Endstufe (9, 10, 13, 14, 15, 16) für große Ausgangsleistungen proportionales Signal und deren anderer Eingang durch ein einem Ausgangssignal der Endstufe (1, 2, 3, 4, 7, 8) für kleine Ausgangsleistungen proportionales Signal angesteuert wird. |
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53 | Active RC filters | US15536504 | 2015-12-14 | US10153742B2 | 2018-12-11 | Phil Corbishley |
An operational amplifier comprises: a first amplifier stage 4 comprising a first differential pair of transistors 8, 10 arranged to receive and amplify a differential input signal 18, 20 thereby providing a first differential output signal 22, 24; and a second amplifier stage 6 comprising a second differential pair of transistors 26, 28 arranged to receive and amplify the first differential output signal 22, 24 thereby providing a second differential output signal 38, 40. | ||||||
54 | Trans-Impedance Amplifier, Chip, and Communications Device | US15894467 | 2018-02-12 | US20180241364A1 | 2018-08-23 | Baoyue Wei; Yuemiao Di |
A trans-impedance amplifier (TIA) includes a first circuit, a second circuit, and a third circuit. Both the first circuit and the second circuit are coupled to a current source, an operational amplifier, and the third circuit. The first circuit is configured to receive a first current, provide a third voltage to the third circuit, perform shape filtering on the first current, and convert the shape filtered first current to a first voltage for output. The second circuit is configured to receive a second current, provide a fourth voltage to the third circuit, perform shape filtering on the second current, and convert the shape filtered second current to a second voltage for output. The third circuit is configured to cooperate with the first circuit and the second circuit in performing shape filtering. The operational amplifier is configured to provide a small-signal virtual ground point to the first circuit. | ||||||
55 | PHOTOELECTRIC CONVERSION DEVICE | US15893013 | 2018-02-09 | US20180241357A1 | 2018-08-23 | Masanori Shibata; Hirotaka Shiomichi |
A photoelectric conversion device is provided. The device comprises a light receiving element, first and second transimpedance amplifiers configured to receive a signal of the light receiving element and output a voltage, a differential operation amplifier configured to perform a differential amplification for outputs of the first and second transimpedance amplifiers and a switching unit. The switching unit includes an output switching unit configured to switch connections between a first state where the light receiving element and the first transimpedance amplifier are connected and a second state where the light receiving element and the second transimpedance amplifier are connected, and a capacitance adjusting unit connected to an input terminal of each of the first and second transimpedance amplifiers and configured to adjust a capacitance value of the first and transimpedance amplifier and/or a capacitance value of the second transimpedance amplifier. | ||||||
56 | Semiconductor device and electronic control system including the same | US15402660 | 2017-01-10 | US10006955B2 | 2018-06-26 | Kazuaki Kurooka; Yasuo Morimoto; Yoshihiro Funato |
According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state. | ||||||
57 | LINEAR CMOS PA WITH LOW QUIESCENT CURRENT AND BOOSTED MAXIMUM LINEAR OUTPUT POWER | US15578058 | 2016-04-28 | US20180159484A1 | 2018-06-07 | Stephen James Franck; Xin Wang; Alireza Oskoui |
The present disclosure relates to a power amplifier (PA) system provided in a semiconductor device and having feed forward gain control. The PA system comprises a transmit path and control circuitry. The transmit path is configured to amplify an input radio frequency (RF) signal and comprises a first tank circuit and a PA stage. The control circuitry is configured to detect a power level associated with the input RF signal and control a first bias signal provided to the PA stage based on a first function of the power level and control a quality factor (Q) of the first tank circuit based on a second function of the power level. | ||||||
58 | METHODS AND APPARATUS FOR REDUCING TRANSIENT GLITCHES IN AUDIO AMPLIFIERS | US15186273 | 2016-06-17 | US20170063309A1 | 2017-03-02 | Kshitij YADAV; Vijayakumar DHANASEKARAN |
An audio amplifier, including: at least a two stage amplifier configured to receive an input signal and output an amplified output signal, the at least a two stage amplifier including at least one stage amplifier and an output stage amplifier; and an auxiliary stage amplifier having an input coupled to an output of the at least one stage amplifier and an input of the output stage amplifier. | ||||||
59 | Feedback Type Voltage Regulator | US14846816 | 2015-09-06 | US20170003699A1 | 2017-01-05 | Yu-Po LIN; Kea-Tiong TANG |
The present invention discloses a feedback type voltage regulator, including a voltage reference circuit for providing a reference voltage, distributed series feedback amplifiers electrically coupled to the voltage reference circuit and a power transistor which gate is electrically connected to the distributed series feedback amplifiers. The distributed series feedback amplifiers comprises three set of amplifiers serially connected with each other, wherein the relation of the gain of the first amplifier (A1), the second amplifier (A2), and the third amplifier (A3) is A1>A2>A3, wherein the relation of the bandwidth of the first amplifier (B1), the second amplifier (B2), and the third amplifier (B3) is B1 | ||||||
60 | Circuits and methods for reducing supply sensitivity in a power amplifier | US14518967 | 2014-10-20 | US09473081B2 | 2016-10-18 | Antonino Scuderi; Aristotele Hadjichristos |
In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range. |