| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 141 | HIGH FREQUENCY AMPLIFIER | US10282000 | 2002-10-29 | US20040080372A1 | 2004-04-29 | Yung-Hung Chen |
| A high frequency amplifier. The amplifier includes two transistors for signal amplification, and input and output matching circuits. There are variable capacitors and resistors in the matching input and output circuits. A received signal strength indicator receives the band-pass filtered intermediate-frequency signal and generates an indication signal corresponding to the amplitude of the received signal. The variable capacitors and resistors are tuned by the indication signal from the received signal strength indicator. Thus, the gain of the high frequency amplifier is automatically controlled. | ||||||
| 142 | CIRCUIT MODULE HAVING DUAL-MODE WIDEBAND POWER AMPLIFIER ARCHITECTURE | US16053806 | 2018-08-03 | US20190052238A1 | 2019-02-14 | Sheng-Hong Yan; Da-Wei Sung; Chen-Yen Ho; Chia-Sheng Peng; Chien-Wei Kuan |
| A circuit module includes a power amplifier, a switch, and a bypass capacitor. The power amplifier has a signal input node coupled to an input signal, a signal output node to generate an output signal, and a power input node coupled to a supply output signal of a supply modulator. The switch is coupled between the power input node of the power amplifier and the bypass capacitor. The bypass capacitor is an equivalently removable bypass capacitor coupled between the switch and a ground level. | ||||||
| 143 | Active Device Which has a High Breakdown Voltage, is Memory-Less, Traps Even Harmonic Signals and Circuits Used Therewith | US15978636 | 2018-05-14 | US20180262172A1 | 2018-09-13 | Farbod Aram |
| An active device and circuits utilised therewith are disclosed. In an aspect the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gale of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals. | ||||||
| 144 | Tunable filter for RF circuits | US14588311 | 2014-12-31 | US10069479B1 | 2018-09-04 | Laurent Desclos |
| A tunable filter is described where the frequency response as well as bandwidth and transmission loss characteristics can be dynamically altered, providing improved performance for transceiver front-end tuning applications. The rate of roll-off of the frequency response can be adjusted to improve performance when used in duplexer applications. The tunable filter topology is applicable for both transmit and receive circuits. A method is described where the filter characteristics are adjusted to account for and compensate for the frequency response of the antenna used in a communication system. | ||||||
| 145 | Doherty amplifier circuits | US15596416 | 2017-05-16 | US10050588B2 | 2018-08-14 | Gerben Willem de Jong; Mark Pieter van der Heijden; Jozef Reinerus Maria Bergervoet; Tony Vanhoucke; Gian Hoogzaad; Ivan Matkov Zahariev |
| A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit. | ||||||
| 146 | Semiconductor device with improved variable gain amplification | US15788505 | 2017-10-19 | US09979364B2 | 2018-05-22 | Masato Osawa; Yasunari Harada; Hideki Kato |
| In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain. | ||||||
| 147 | Source switched split LNA | US15342016 | 2016-11-02 | US09973149B2 | 2018-05-15 | Emre Ayranci; Miles Sanner |
| A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention. | ||||||
| 148 | Compensation circuit of power amplifier and associated compensation method | US15647275 | 2017-07-12 | US09960947B2 | 2018-05-01 | Chien-Cheng Lin; Ming-Da Tsai |
| A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result. | ||||||
| 149 | Control systems and methods for power amplifiers operating in envelope tracking mode | US15046267 | 2016-02-17 | US09960736B2 | 2018-05-01 | Dan William Nobbe; Jeffrey A. Dykstra; Chris Olson; James S. Cable |
| Control systems and methods for power amplifiers operating in envelope tracking mode are presented. A set of corresponding functions and modules are described and various possible system configurations using such functions and modules are presented. | ||||||
| 150 | Sensor amplifier arrangement and method of amplifying a sensor signal | US14933068 | 2015-11-05 | US09948250B2 | 2018-04-17 | Thomas Fröhlich; Matthias Steiner |
| A sensor amplifier arrangement includes an amplifier having a signal input to receive a sensor signal and a signal output to provide an amplified sensor signal, and a feedback path that couples the signal output to the signal input and provides a feedback current that is an attenuated signal of the amplified sensor signal and is inverted with respect to the sensor signal. | ||||||
| 151 | Ultra-low-power RF receiver frontend with tunable matching networks | US15098784 | 2016-04-14 | US09929760B2 | 2018-03-27 | Hong-Lin Chu; Hsieh-Hung Hsieh; Tzu-Jin Yeh |
| A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array. | ||||||
| 152 | LNA with programmable linearity | US15272103 | 2016-09-21 | US09929701B1 | 2018-03-27 | Hossein Noori; Chih-Chieh Cheng |
| A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention. | ||||||
| 153 | COMPENSATION CIRCUIT OF POWER AMPLIFIER AND ASSOCIATED COMPENSATION METHOD | US15647275 | 2017-07-12 | US20180069742A1 | 2018-03-08 | Chien-Cheng Lin; Ming-Da Tsai |
| A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result. | ||||||
| 154 | SEMICONDUCTOR DEVICE | US15788505 | 2017-10-19 | US20180062595A1 | 2018-03-01 | Masato Osawa; Yasunari Harada; Hideki Kato |
| In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain. | ||||||
| 155 | Source Switched Split LNA | US15342016 | 2016-11-02 | US20180019710A1 | 2018-01-18 | Emre Ayranci; Miles Sanner |
| A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention. | ||||||
| 156 | Ultra-Low-Power RF Receiver Frontend With Tunable Matching Networks | US15098784 | 2016-04-14 | US20170302316A1 | 2017-10-19 | Hong-Lin CHU; Hsieh-Hung HSIEH; Tzu-Jin YEH |
| A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array. | ||||||
| 157 | Amplifiers operating in envelope tracking mode or non-envelope tracking mode | US14821501 | 2015-08-07 | US09729107B2 | 2017-08-08 | Dan William Nobbe; Jeffrey A. Dykstra; Chris Olson; James S. Cable |
| Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode. | ||||||
| 158 | POWER AMPLIFIER SYSTEM AND ASSOCIATED CONTROL CIRCUIT AND CONTROL METHOD | US15348956 | 2016-11-10 | US20170207758A1 | 2017-07-20 | Chien-Wei Tseng; Ming-Da Tsai |
| A control circuit of a power amplifier includes a peak detector, a first comparator, a first current source, a second comparator, a second current source and a bias circuit. The peak detector is arranged for detecting an amplitude of an input signal. The first comparator is arranged for comparing the amplitude of the input signal with a first threshold to generate a first comparing result. The first current source is arranged for generating a first current according to the first comparing result The second comparator is arranged for comparing the amplitude of the input signal with a second threshold to generate a second comparing result. The second current source is arranged for generating a second current according to the second comparing result. The bias circuit is arranged for generating a bias voltage according to the first current and the second current to the power amplifier. | ||||||
| 159 | Power amplifier | US14676748 | 2015-04-01 | US09590561B2 | 2017-03-07 | Li Cai; Juan Xie; Poh Boon Leong |
| An apparatus includes a differential amplifier. The differential amplifier includes a first side circuit configured to receive a first input signal, a second side circuit configured to receive a second input signal, and a resonant tank circuit coupled between the first and second side circuits. A first capacitor and first switch may be provided in series between a source and drain of a cascode transistor. A second capacitor and second switch may be provided in series between a source and drain of an input transistor. A method includes receiving a first input signal by a first side circuit, receiving a second input signal by a second side circuit, controlling a resource of a resonant tank circuit, and outputting an output signal according to the first and second input signals. The resource of the resonant tank circuit may be controlled according to a transmission mode, frequency band, or both. | ||||||
| 160 | POWER AMPLIFIERS WITH TUNABLE LOADLINE MATCHING NETWORKS | US15230205 | 2016-08-05 | US20170040948A1 | 2017-02-09 | Chris Levesque |
| A power amplifier is described. The power amplifier includes at least a first power amplifier stage coupled with a power supply. The first power amplifier stage is configured to adjust a first output power of the first power amplifier stage based on a power supply voltage of the power supply. The power amplifier also includes at least a first tunable loadline matching network. The first tunable loadline matching network is configured to adjust a loadline value of the power amplifier. The first tunable loadline matching network includes at least a first set of metal oxide semiconductor variable capacitor arrays. | ||||||
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