| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | MEMORYLESS ACTIVE DEVICE WHICH TRAPS EVEN HARMONIC SIGNALS | EP15809735 | 2015-06-19 | EP3158642A4 | 2018-03-14 | ARAM FARBOD |
| An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memoryless and traps even harmonic signals. | ||||||
| 42 | COMPENSATION CIRCUIT OF POWER AMPLIFIER AND ASSOCIATED COMPENSATION METHOD | EP17182848.6 | 2017-07-24 | EP3291444A1 | 2018-03-07 | LIN, Chien-Cheng; TSAI, Ming-Da |
A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.
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| 43 | AMPLIFIER LINEARIZATION | EP15184887.6 | 2015-09-11 | EP3142250A1 | 2017-03-15 | Jansson, Lars Gustaf |
An amplifier (150) comprising a first transistor (101) and a second transistor (102) connected in parallel. The second transistor (102) is configured to linearize the amplifier (150) by reducing third order non-linearity from the first transistor (101) by operating in the sub-threshold mode when the first transistor is biased in a saturation mode. A programmable voltage divider (120) is provided connecting an input node (111, 112) to the gate of the first transistor (101) or the gate of the second transistor (102) for tuning an amount of input signal applied at the gate of the first transistor (101) relative to an amount of the input signal applied at the gate of the second transistor (102).
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| 44 | Biomedical acquisition system with motion artifact reduction | EP12191680.3 | 2012-11-07 | EP2591720A1 | 2013-05-15 | Yazicioglu, Refet Firat; Kim, Sunyoung |
A system (100) for the analysis of ECG signals comprising: at least one readout channel (110), configured to receive an analogue ECG signal (101) acquired from at least one electrode attached to a body; and to extract an analogue measured ECG signal (120) and analogue electrode-skin impedance signals (121, 122); at least one ADC (130), configured to convert those extracted analogue signals at the readout channel into digital signals; a digital adaptive filter unit (180), configured to calculate a digital motion artifact estimate (181) based on said digital versions of the measured ECG signal and the electrode-skin impedance signals; at least one DAC (131), configured to convert said digital motion artifact estimate into an analogue signal; and a feedback loop (140) for sending said analogue motion artifact estimate signal back to the readout channel (101) configured to deduct said analogue motion artifact estimate signal from said analogue measured ECG signal.
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| 45 | Analog circuit | EP09179509.6 | 2006-03-20 | EP2166667B1 | 2012-02-01 | Shigematsu, Hisao |
| 46 | Analog circuit | EP10193030.3 | 2006-03-20 | EP2296268A1 | 2011-03-16 | Shigematsu, Hisao |
An analog circuit is provided, comprising: an oscillation transistor; and a negative resistance change circuit changing negative resistance for said oscillation transistor, wherein said negative resistance change circuit comprises a variable resistor circuit connected to a source of said oscillation transistor.
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| 47 | Analog circuit | EP09179509.6 | 2006-03-20 | EP2166667A2 | 2010-03-24 | Shigematsu, Hisao |
An analog circuit is provided, comprising an input transistor and an input capacitance change circuit changing input capacitance of said input transistor. The input capacitance change circuit comprises at least one of a variable resistor circuit connected to a source of said input transistor and a variable capacitor circuit connected to the source off said input transistor.
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| 48 | VARIABLE GAIN AMPLIFIER AND ITS CONTROL METHOD | EP05787586 | 2005-09-30 | EP1931027A4 | 2009-11-11 | ARAI TOMOYUKI |
| 49 | ANALOG CIRCUIT | EP06729563.4 | 2006-03-20 | EP1998439A1 | 2008-12-03 | SHIGEMATSU, Hisao |
A resistor (9-1) and a resistor (11-1) are connected in parallel with each other between a source of an input transistor (7-1) and the ground. A switch (12-1) is provided between the resistor (11-1) and the source. A variable resistor circuit may be constituted by the resistor (9-1), the resistor (11-1) and the switch (12-1). Further, a capacitor (10-1) and a variable capacitor (13-1) are connected in series with each other between the source and the ground. A control terminal (14-1) to which a voltage is applied when capacitance of the variable capacitor (13-1) is controlled is provided between the capacitor (10-1) and the variable capacitor (13-1). A variable capacitor circuit may be constituted by the capacitor (10-1) and the variable capacitor (13-1). An input capacitance change circuit may be constituted by the variable resistor circuit and the variable capacitor circuit. |
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| 50 | CIRCUIT FOR IMPROVED DIFFERENTIAL AMPLIFIER AND OTHER APPLICATIONS | EP04760211.5 | 2004-03-25 | EP1625656B1 | 2007-11-07 | BROWN, Albert, Warren |
| Differential amplifiers and phase-splitting circuits incorporate voltage-transfer or current-transfer devices of different conductivity types that are connected in series between two different potentials. The current flowing through the two devices is responsive to input signals provided to either or both of the devices. The two devices may be of different types such as bipolar transistors, field-effect transistors, vacuum tubes, triacs and silicon controlled rectifiers. Specific implementations include amplifiers with very low input capacitance and very low second harmonic distortion, multi-state memory cells, detectors and voltage regulators. | ||||||
| 51 | HIGH-LINEARITY LOW NOISE AMPLIFIER | PCT/US2010030027 | 2010-04-06 | WO2010120594A2 | 2010-10-21 | DUSTER JON S; TAYLOR STEWART S |
| Embodiments of a high-linearity low-noise amplifier (LNA) are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier. The cascode amplifier may include integrated notch filters to attenuate undesired signals. The cascode amplifier may operate from a large power supply when blockers are present to avoid voltage swing compression at its output. The cascode amplifier may be biased and designed to operate in a class AB mode to produce linear output current to avoid current compression or excessive current expansion. | ||||||
| 52 | MEMS TRANSDUCER AMPLIFIERS | US15916597 | 2018-03-09 | US20180270588A1 | 2018-09-20 | Hynek Saman; James Thomas Deas |
| This applications relates to methods and apparatus for amplifying signals from capacitive transducers, in particular MEMS transducers such as MEMS capacitive microphones. An amplifier circuit has a transducer biasing node (102) for outputting a transducer bias voltage for biasing the capacitive transducer (101) and a signal node (103) for receiving the input signal (Vin). An amplifier arrangement (108) comprising a feedback resistor network (304, 305) provides an amplified output signal (Vout). A voltage buffer (306) provides a buffered bias voltage at a buffer node (307) which is connected to a terminal of the feedback resistor network, to at least partly define the quiescent level of the output signal. The buffer node (307) is electrically coupled to the transducer biasing node (102) via a capacitance (106) which may form part of a bias filter. | ||||||
| 53 | Power amplifier system and associated control circuit and control method | US15348956 | 2016-11-10 | US10056869B2 | 2018-08-21 | Chien-Wei Tseng; Ming-Da Tsai |
| A control circuit of a power amplifier includes a peak detector, a first comparator, a first current source, a second comparator, a second current source and a bias circuit. The peak detector is arranged for detecting an amplitude of an input signal. The first comparator is arranged for comparing the amplitude of the input signal with a first threshold to generate a first comparing result. The first current source is arranged for generating a first current according to the first comparing result The second comparator is arranged for comparing the amplitude of the input signal with a second threshold to generate a second comparing result. The second current source is arranged for generating a second current according to the second comparing result. The bias circuit is arranged for generating a bias voltage according to the first current and the second current to the power amplifier. | ||||||
| 54 | Fast settling capacitive gain amplifier circuit | US15600484 | 2017-05-19 | US10044327B2 | 2018-08-07 | Hanqing Wang; Gerard Mora-Puchalt |
| A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase. | ||||||
| 55 | Low-noise amplifier (LNA) with capacitive attenuator | US15400078 | 2017-01-06 | US10033340B1 | 2018-07-24 | Bassel Hanafi; Sherif Abdelhalem; Hasnain Lakdawala |
| Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator. | ||||||
| 56 | LOW-NOISE AMPLIFIER (LNA) WITH CAPACITIVE ATTENUATOR | US15400078 | 2017-01-06 | US20180198428A1 | 2018-07-12 | Bassel HANAFI; Sherif ABDELHALEM; Hasnain LAKDAWALA |
| Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator. | ||||||
| 57 | Active device which has a high breakdown voltage, is memory-less, traps even harmonic signals and circuits used therewith | US15367995 | 2016-12-02 | US10003314B2 | 2018-06-19 | Farbod Aram |
| An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals. | ||||||
| 58 | LOW-NOISE AMPLIFIER AND ELECTRONIC DEVICE | US15836115 | 2017-12-08 | US20180102745A1 | 2018-04-12 | Saneaki ARIUMI |
| Provided is a low-noise amplifier that can effectively suppress noise included in an input signal. A low-noise amplifier according to an embodiment of the present invention amplifies a reception signal in a predetermined frequency band from an antenna. The low-noise amplifier includes an input terminal, an output terminal, a field effect transistor, and a branch circuit. The branch circuit is branched from a circuit connecting the input terminal or the output terminal to the field effect transistor. The branch circuit is connected to the elastic wave resonator. | ||||||
| 59 | Amplifier dynamic bias adjustment for envelope tracking | US15040952 | 2016-02-10 | US09941843B2 | 2018-04-10 | Dan William Nobbe; Jeffrey A. Dykstra; Chris Olson; James S. Cable |
| An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor. | ||||||
| 60 | FAST SETTLING CAPACITIVE GAIN AMPLIFIER CIRCUIT | US15600484 | 2017-05-19 | US20180076779A1 | 2018-03-15 | Hanqing Wang; Gerard Mora-Puchalt |
| A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase. | ||||||
