| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 缓冲放大器电路 | CN201480027520.X | 2014-03-14 | CN105247783A | 2016-01-13 | 李海升 |
| 用电压增益基本上等于一的缓冲放大器实现的放大器电路。在一个示例中，通过跨缓冲放大器的输入端子和输出端子施加输入源来实现连续时间放大器。在另一个示例中，实现离散时间放大器。在采样阶段期间，对至少一个输入电压进行采样，在传输阶段期间，至少一个电容器跨缓冲放大器的输入端子和输出端子被耦合来实现放大。 | ||||||
| 2 | 放大器 | CN201280024061.0 | 2012-05-18 | CN103563250A | 2014-02-05 | J·J·埃基南; J·J·瑞基; J·K·考科武里 |
| 本发明涉及一种可配置低噪声放大器电路，该可配置低噪声放大器电路可在第一拓扑和第二拓扑之间进行配置，在第一拓扑中，低噪声放大器电路包括简并电感，由此低噪声放大器电路作为电感简并的低噪声放大器进行操作，在第二拓扑中，低噪声放大器电路包括反馈电阻，由此低噪声放大器电路作为电阻反馈低噪声放大器进行操作。 | ||||||
| 3 | 射频集成电路 | CN201280034977.4 | 2012-05-18 | CN103843248A | 2014-06-04 | J·J·埃基南; J·J·瑞基; J·K·考科武里 |
| 本发明的实施例涉及可配置RFIC。在一个实施例中，提供一种包括一个或者多个可配置低噪声放大器电路的可配置射频集成电路（RFIC），所述一个或者多个可配置低噪声放大器电路中的每个可配置低噪声放大器电路在以下拓扑之间可配置：内部输入阻抗匹配拓扑，在内部输入阻抗匹配拓扑中，相应低噪声放大器电路包括适于将相应低噪声放大器的输入阻抗与给定的输入匹配的一个或者多个内部输入阻抗匹配部件，该一个或者多个内部输入阻抗匹配部件位于相应低噪声放大器电路内部；以及与该内部输入阻抗匹配拓扑不同的拓扑。 | ||||||
| 4 | ブーストまたはデブーストされたソースディジェネレーションインダクタンスをもつ増幅器 | JP2016506359 | 2014-04-01 | JP2016514926A | 2016-05-23 | シュ、ルイ; チャン、リ−チュン |
| ブーストまたはデブーストされたソースディジェネレーションインダクタンスをもつ増幅器が開示される。例示的な設計では、装置は増幅器回路とフィードバック回路とを含む。増幅器回路は、入力信号を受信し、出力信号を与え、ソースディジェネレーションインダクタを含む。フィードバック回路は増幅器回路のノードとソースディジェネレーションインダクタとの間に結合される。フィードバック回路は、増幅器回路とフィードバック回路とを含む増幅器の入力インピーダンスを変化させるためにフィードバックを与える。フィードバック回路はプログラム可能であり得、フィードバックを与えるために有効にされるか、またはフィードバックを与えないために無効にされ得る。代替的に、フィードバック回路は、常に、フィードバックを与えるために有効にされ得る。いずれの場合も、フィードバック回路は、増幅器のための可変入力インピーダンスを与えるための可変利得を有し得る。 | ||||||
| 5 | ブーストまたはデブーストされたソースディジェネレーションインダクタンスをもつ増幅器 | JP2016506359 | 2014-04-01 | JP5992648B2 | 2016-09-14 | シュ、ルイ; チャン、リ−チュン |
| 6 | Arithmetic amplifier provided with null offset digital adjustment possible | JP19811990 | 1990-07-27 | JPH0365806A | 1991-03-20 | JIYASUUINDAA ESU JIYANDEYUU; AIRA MIRAA |
| PURPOSE: To enable re-adjusting of a null offset by amplifying difference between first and second signals in inversion and non-inversion inputs. CONSTITUTION: A system is constituted of a first current source which provides first current to a differential input stage. The differential input stage is provided with the inversion and the non-inversion inputs which respectively amplify the difference between the first and the second signals in the inversion input and the non-inversion input. The second current source is provided with second and third current and second current is digitally adjusted for the reference current of a current frequency devider so as to give influence on the null offset between the inversion input and the non-inversion input. The second current source is connected to a current frequency divider 9 which receives a part of second current and unbalance occurs between second current and third current. A load stage is provided by having a driver node and connected to the differential input stage for supplying an amplifier signal to the second current source and the driver node. Thus, null offset is quickly and repeatedly adjusted. COPYRIGHT: (C)1991,JPO | ||||||
| 7 | SELF-REGULATED REFERENCE FOR SWITCHED CAPACITOR CIRCUIT | US15166066 | 2016-05-26 | US20170077883A1 | 2017-03-16 | Wen-Hua Chang |
| A switched-capacitor circuit comprising a differential operational amplifier and a feedback circuit is described. In some embodiments, the feedback circuit may be configured to provide a reference voltage that is insensitive to temperature and/or process variations. In some embodiments, the feedback circuit may be configured to mitigate the time delay associated with one or more capacitors of the switched-capacitor circuit. The switched-capacitor circuit may be controlled by a pair of control signals. During a first phase, one or more capacitors may be charged, or discharged, through an input signal. During a second phase, the electric charge of the one or more capacitors may be retained. | ||||||
| 8 | Zero drift, limitless and adjustable reference voltage generation | US15094459 | 2016-04-08 | US09552003B2 | 2017-01-24 | Dan Vinge Madsen; Stig Alnøe Lindemann |
| A circuit for generation of a reference voltage for an electronic system, which circuit comprises at least one digital buffer (U21, U31, U32, U41, U51), a low pass filter (R21, C21; R31, C31; R41, C41; R51, C51) and an operational amplifier (OA21, OA31, OA41, OA51)), which circuit is adapted to revive an input in the form of a bandgap reference voltage into the digital buffer, which digital buffer is adapted to receive a digital input from a Pulse Width Modulated (PWM) signal, which digital buffer is adapted to generate an output signal adapted to be fed to the low pass filter, which output signal after filtration is adapted to be fed to a positive input terminal of the operational amplifier, which operational amplifier comprises a feedback circuit, which feedback circuit comprises at least one capacitor (C22, C32, C44, C54) adapted to be connected from an output terminal of the operational amplifier towards a negative input terminal of the operational amplifier so as to form an integrator, wherein the feedback circuit further comprises at least one chopped signal path (R22, S21; R33, R34, S32; R33, R35, C35, S31), which chopped signal is adapted to be modulated by the output signal of the digital buffer. | ||||||
| 9 | Buffer Amplifier Circuit | US14723044 | 2015-05-27 | US20150280658A1 | 2015-10-01 | Hae-Seung Lee |
| Amplifier circuits implemented with a buffer amplifier with a voltage gain substantially equal to one. In one example, a continuous-time amplifier is implemented by applying the input source across the input and the output terminals of the buffer amplifier. In another example, a discrete-time amplifier is implemented. During the sampling phase at least one input voltage is sampled, and during the transfer phase at least one capacitor is coupled across the input and the output terminals of a buffer amplifier to effectuate an amplification. | ||||||
| 10 | APPARATUS AND METHOD FOR LOW NOISE AMPLIFICATION | US13528222 | 2012-06-20 | US20130057346A1 | 2013-03-07 | Jonne Juhani RIEKKI; Jari Johannes HEIKKINEN; Jouni Kristian KAUKOVUORI |
| Embodiments provide an amplifier and a method for using and manufacturing said amplifier that incorporate an impedance matching stage, a feedback circuit, and a gain stage. The impedance matching stage is coupled to the feedback circuit wherein the feedback circuit provides a compensated second bias voltage for the impedance matching stage. The output of the impedance matching stage is used to set an input bias voltage for both the impedance matching stage and the gain stage. The output of the impedance matching stage is also used, together with the output of the gain stage, to produce an output of the amplifier. A signal reuse stage may be provided between the output of the impedance matching stage and the output of the amplifier. | ||||||
| 11 | Amplifier | US13111423 | 2011-05-19 | US08378748B2 | 2013-02-19 | Jari Johannes Heikkinen; Jonne Juhani Riekki; Jouni Kristian Kaukovuori |
| The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier. | ||||||
| 12 | CORRELATED DOUBLE SAMPLING INTEGRATING CIRCUIT | US16139028 | 2018-09-22 | US20190027229A1 | 2019-01-24 | Mengwen ZHANG; Chang ZHAN |
| A correlated double sampling integrating circuit is provided. The circuit includes: a sampling and holding module, an energy storage unit and a feedback module. The sampling and holding module is configured to perform sampling and holding for different input signals. The energy storage unit is configured to store charges corresponding to the input signals upon the sampling and holding to generate node signals, and the feedback module is configured to form a negative feedback loop with the energy storage unit to control node signals at an integrating stage to keep consistent with node signals at a resetting stage and prevent output jump of the correlated double sampling integrating circuit. The correlated double sampling integrating circuit reduces noise, and prevents or weakens output jump of the correlated double sampling integrating circuit caused by the increase of the count of integrations. | ||||||
| 13 | Buffer amplifier circuit | US14210958 | 2014-03-14 | US09154089B2 | 2015-10-06 | Hae-Seung Lee |
| Amplifier circuits implemented with a buffer amplifier with a voltage gain substantially equal to one. In one example, a continuous-time amplifier is implemented by applying the input source across the input and the output terminals of the buffer amplifier. In another example, a discrete-time amplifier is implemented. During the sampling phase at least one input voltage is sampled, and during the transfer phase at least one capacitor is coupled across the input and the output terminals of a buffer amplifier to effectuate an amplification. | ||||||
| 14 | Amplifiers with boosted or deboosted source degeneration inductance | US13857031 | 2013-04-04 | US09124228B2 | 2015-09-01 | Rui Xu; Li-Chung Chang |
| Amplifiers with boosted or deboosted source degeneration inductance are disclosed. In an exemplary design, an apparatus includes an amplifier circuit and a feedback circuit. The amplifier circuit receives an input signal and provides an output signal and includes a source degeneration inductor. The feedback circuit is coupled between a node of the amplifier circuit and the source degeneration inductor. The feedback circuit provides feedback to vary an input impedance of an amplifier including the amplifier circuit and the feedback circuit. The feedback circuit may be programmable and may be enabled to provide feedback or disabled to provide no feedback. Alternatively, the feedback circuit may always be enabled to provide feedback. In either case, the feedback circuit may have a variable gain to provide a variable input impedance for the amplifier. | ||||||
| 15 | Buffer Amplifier Circuit | US14210958 | 2014-03-14 | US20140266845A1 | 2014-09-18 | Hae-Seung Lee |
| Amplifier circuits implemented with a buffer amplifier with a voltage gain substantially equal to one. In one example, a continuous-time amplifier is implemented by applying the input source across the input and the output terminals of the buffer amplifier. In another example, a discrete-time amplifier is implemented. During the sampling phase at least one input voltage is sampled, and during the transfer phase at least one capacitor is coupled across the input and the output terminals of a buffer amplifier to effectuate an amplification. | ||||||
| 16 | Amplifier | US13271705 | 2011-10-12 | US08432217B2 | 2013-04-30 | Jonne Juhani Riekki; Jari Johannes Heikkinen; Jouni Kristian Kaukovuori |
| A configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance stage whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a common-gate low noise amplifier stage whereby the low noise amplifier circuit operates as a common-gate low noise amplifier. The second topology includes one or more internal input impedance matching components and the first topology does not include the one or more internal input impedance matching components. | ||||||
| 17 | Sample-and-hold amplifier | US13050541 | 2011-03-17 | US08390372B2 | 2013-03-05 | Berry Anthony Johannus Buter; Hans Van de Vel |
| A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample-and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation. | ||||||
| 18 | Amplifier | US13111423 | 2011-05-19 | US20120293262A1 | 2012-11-22 | Jari Johannes HEIKKINEN; Jonne Juhani Riekki; Jouni Kristian Kaukovuori |
| The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier. | ||||||
| 19 | SAMPLE-AND-HOLD AMPLIFIER | US13050541 | 2011-03-17 | US20120068766A1 | 2012-03-22 | Berry Anthony Johannus Buter; Hans Van de Vel |
| A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample-and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation. | ||||||
| 20 | Operational amplifier having improved digitally adjusted null offset | US386097 | 1989-07-28 | US4933643A | 1990-06-12 | Jaswinder S. Jandu; Ira Miller |
| An operational amplifier is provided having a null offset that may be digitally adjusted quickly and accurately. The operational amplifier includes a cascode current mirror in an output stage wherein a small portion of current in the cascode current mirror is diverted away into a digitally controlled current divider. The more current that is diverted away, the larger the differential voltage that is created between the inverting and noninverting inputs of the operational amplifier. The current is increased until the output of the operational amplifier switches from the positive supply voltage to the ground supply voltage or vise versa. Additionally, a compensation capacitor at the output of the operational amplifier is switched out of the circuit during adjustment to speed up the null offset adjustment. Because the current being adjusted is not directly at the inputs of the operational amplifier the common mode input range is not deteriorated. | ||||||
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