| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 21 | AMPLIFICATION CIRCUIT | EP16885458 | 2016-07-19 | EP3261250A4 | 2018-07-04 | ZHANG MENGWEN |
| The present application provides an amplifying circuit comprising a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage, the common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage, the common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit provided in the present application can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback. | ||||||
| 22 | ZERO DRIFT, LIMITLESS AND ADJUSTABLE REFERENCE VOLTAGE GENERATION | EP16164181.6 | 2016-04-07 | EP3079256A1 | 2016-10-12 | LINDEMANN, Stig Alnøe; MADSEN, Dan Vinge |
A circuit for generation of a reference voltage for an electronic system, which circuit comprises at least one digital buffer (U21, U31, U32, U41, U51), a low pass filter (R21, C21; R31, C31; R41, C41; R51, C51) and an operational amplifier (OA21, OA31, OA41, OA51)), which circuit is adapted to revive an input in the form of a bandgap reference voltage into the digital buffer, which digital buffer is adapted to receive a digital input from a Pulse Width Modulated (PWM) signal, which digital buffer is adapted to generate an output signal adapted to be fed to the low pass filter, which output signal after filtration is adapted to be fed to a positive input terminal of the operational amplifier, which operational amplifier comprises a feedback circuit, which feedback circuit comprises at least one capacitor (C22, C32, C44, C54) adapted to be connected from an output terminal of the operational amplifier towards a negative input terminal of the operational amplifier so as to form an integrator, wherein the feedback circuit further comprises at least one chopped signal path (R22, S21; R33, R34, S32; R33, R35, C35, S31), which chopped signal is adapted to be modulated by the output signal of the digital buffer.
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| 23 | BUFFER AMPLIFIER CIRCUIT | EP14768045 | 2014-03-14 | EP2974008A4 | 2016-09-07 | LEE HAE-SEUNG |
| The invention relates to a discrete-time amplifier circuit (300) operable in a sampling phase and an amplification phase. The amplifier circuit comprises a plurality of switches (S1, S2); a first capacitor (C1) having a first terminal and a second terminal; a second capacitor (C2) having a first terminal and a second terminal; and a first buffer amplifier (BA) having a voltage gain equal to 1-ε, where ε<<1, the first buffer amplifier having an input terminal (301) and an output terminal (302). During the sampling phase, the plurality of switches are configured to couple a first input voltage (VIN) to the first terminal of the first capacitor and a second input voltage (VREF) to the first terminal of the second capacitor. Further, during the amplification phase, the plurality of switches are configured to couple the first terminals of the first and the second capacitors to the input terminal of the first buffer amplifier and the second terminals of the first and second capacitors to the output terminal of the first buffer amplifier. | ||||||
| 24 | A sample-and-hold amplifier | EP10250528.6 | 2010-03-19 | EP2367285A1 | 2011-09-21 | van de Vel, Hans; Buter, Berry Anthony Johannus |
A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample,and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation.
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| 25 | 부스팅되거나 디부스팅된 소스 디제너레이션 인덕턴스를 갖는 증폭기들 | KR1020157031061 | 2014-04-01 | KR1020150139553A | 2015-12-11 | 수,루이; 창,리-청 |
| 부스팅되거나디부스팅된소스디제너레이션인덕턴스를갖는증폭기들이개시된다. 예시적인설계에서, 장치는증폭기회로및 피드백회로를포함한다. 증폭기회로는입력신호를수신하고출력신호를제공하며소스디제너레이션인덕터를포함한다. 피드백회로는증폭기회로의노드와소스디제너레이션인덕터간에커플링된다. 피드백회로는증폭기회로및 피드백회로를포함하는증폭기의입력임피던스를변동시키기위한피드백을제공한다. 피드백회로는프로그래밍가능할수 있고, 피드백을제공하도록인에이블되거나피드백을제공하지않도록디스에이블될수 있다. 대안적으로, 피드백회로는피드백을제공하도록항상인에이블될수 있다. 어느경우든, 피드백회로는증폭기에대한가변입력임피던스를제공하도록가변이득을가질수 있다. | ||||||
| 26 | Digital-To-Analog Converter Circuit, Corresponding Device and Method | US16020678 | 2018-06-27 | US20190013819A1 | 2019-01-10 | Luigino D'Alessio; Germano Nicollini |
| In some embodiments, a circuit for use in devices involving digital-to-analog conversion of signals includes: a capacitive digital-to-analog converter array and an amplifier. The capacitive digital-to-analog converter includes an input port for receiving a digital input signal and an output port. The amplifier includes capacitive feedback loops that include a first capacitor coupling the output of the amplifier with the input of the amplifier and a second capacitor coupled to the output port of the digital-to-analog converter array at the input of the amplifier. The circuit further includes a set of switches that include a first switch and a second switch coupled with opposed ends of the second capacitor at the input and at the output of the amplifier, respectively. | ||||||
| 27 | Optimized multi gain LNA enabling low current and high linearity including highly linear active bypass | US15479173 | 2017-04-04 | US10038418B1 | 2018-07-31 | Emre Ayranci; Miles Sanner |
| An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET. | ||||||
| 28 | Amplifying circuit | US15657618 | 2017-07-24 | US09973146B2 | 2018-05-15 | Mengwen Zhang |
| An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback. | ||||||
| 29 | Self-regulated reference for switched capacitor circuit | US15166066 | 2016-05-26 | US09847763B2 | 2017-12-19 | Wen-Hua Chang |
| A switched-capacitor circuit comprising a differential operational amplifier and a feedback circuit is described. In some embodiments, the feedback circuit may be configured to provide a reference voltage that is insensitive to temperature and/or process variations. In some embodiments, the feedback circuit may be configured to mitigate the time delay associated with one or more capacitors of the switched-capacitor circuit. The switched-capacitor circuit may be controlled by a pair of control signals. During a first phase, one or more capacitors may be charged, or discharged, through an input signal. During a second phase, the electric charge of the one or more capacitors may be retained. | ||||||
| 30 | AMPLIFYING CIRCUIT | US15657618 | 2017-07-24 | US20170331432A1 | 2017-11-16 | Mengwen ZHANG |
| An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback. | ||||||
| 31 | High linearity structure for amplifier | US14812867 | 2015-07-29 | US09641128B2 | 2017-05-02 | Chien-Chung Yang; Vijayakumar Dhanasekaran |
| An apparatus includes an input amplifier stage and a switch that has a first terminal at a virtual ground input of the input amplifier stage. | ||||||
| 32 | METHODS AND APPARATUS FOR REDUCING TRANSIENT GLITCHES IN AUDIO AMPLIFIERS | US15186273 | 2016-06-17 | US20170063309A1 | 2017-03-02 | Kshitij YADAV; Vijayakumar DHANASEKARAN |
| An audio amplifier, including: at least a two stage amplifier configured to receive an input signal and output an amplified output signal, the at least a two stage amplifier including at least one stage amplifier and an output stage amplifier; and an auxiliary stage amplifier having an input coupled to an output of the at least one stage amplifier and an input of the output stage amplifier. | ||||||
| 33 | DIFFERENTIAL VOLTAGE REFERENCE BUFFER WITH RESISTOR CHOPPING | US14830584 | 2015-08-19 | US20170054415A1 | 2017-02-23 | Dongyang Tang; Vijayakumar Dhanasekaran |
| A voltage reference buffer circuit, including: an amplifier having input terminals and output terminals; a plurality of current sources coupled to the input terminals of the amplifier, the plurality of current sources including a plurality of degeneration resistors coupled to a first plurality of voltage supplies; and a degeneration resistor chopping module comprising a first and second plurality of switches coupled to the plurality of degeneration resistors. | ||||||
| 34 | HIGH LINEARITY STRUCTURE FOR AMPLIFIER | US14812867 | 2015-07-29 | US20170033744A1 | 2017-02-02 | Chien-Chung Yang; Vijayakumar Dhanasekaran |
| An apparatus includes an input amplifier stage and a switch that has a first terminal at a virtual ground input of the input amplifier stage. | ||||||
| 35 | Zero Drift, Limitless and Adjustable Reference Voltage Generation | US15094459 | 2016-04-08 | US20160299519A1 | 2016-10-13 | Dan Vinge Madsen; Stig Alnøe Lindemann |
| A circuit for generation of a reference voltage for an electronic system, which circuit comprises at least one digital buffer (U21, U31, U32, U41, U51), a low pass filter (R21, C21; R31, C31; R41, C41; R51, C51) and an operational amplifier (OA21, OA31, OA41, OA51)), which circuit is adapted to revive an input in the form of a bandgap reference voltage into the digital buffer, which digital buffer is adapted to receive a digital input from a Pulse Width Modulated (PWM) signal, which digital buffer is adapted to generate an output signal adapted to be fed to the low pass filter, which output signal after filtration is adapted to be fed to a positive input terminal of the operational amplifier, which operational amplifier comprises a feedback circuit, which feedback circuit comprises at least one capacitor (C22, C32, C44, C54) adapted to be connected from an output terminal of the operational amplifier towards a negative input terminal of the operational amplifier so as to form an integrator, wherein the feedback circuit further comprises at least one chopped signal path (R22, S21; R33, R34, S32; R33, R35, C35, S31), which chopped signal is adapted to be modulated by the output signal of the digital buffer. | ||||||
| 36 | Buffer amplifier circuit | US14723044 | 2015-05-27 | US09356565B2 | 2016-05-31 | Hae-Seung Lee |
| Amplifier circuits implemented with a buffer amplifier with a voltage gain substantially equal to one. In one example, a continuous-time amplifier is implemented by applying the input source across the input and the output terminals of the buffer amplifier. In another example, a discrete-time amplifier is implemented. During the sampling phase at least one input voltage is sampled, and during the transfer phase at least one capacitor is coupled across the input and the output terminals of a buffer amplifier to effectuate an amplification. | ||||||
| 37 | AMPLIFIERS WITH BOOSTED OR DEBOOSTED SOURCE DEGENERATION INDUCTANCE | US13857031 | 2013-04-04 | US20140300417A1 | 2014-10-09 | Rui Xu; Li-Chung Chang |
| Amplifiers with boosted or deboosted source degeneration inductance are disclosed. In an exemplary design, an apparatus includes an amplifier circuit and a feedback circuit. The amplifier circuit receives an input signal and provides an output signal and includes a source degeneration inductor. The feedback circuit is coupled between a node of the amplifier circuit and the source degeneration inductor. The feedback circuit provides feedback to vary an input impedance of an amplifier including the amplifier circuit and the feedback circuit. The feedback circuit may be programmable and may be enabled to provide feedback or disabled to provide no feedback. Alternatively, the feedback circuit may always be enabled to provide feedback. In either case, the feedback circuit may have a variable gain to provide a variable input impedance for the amplifier. | ||||||
| 38 | Apparatus and method for low noise amplification | US13528222 | 2012-06-20 | US08436684B2 | 2013-05-07 | Jonne Juhani Riekki; Jari Johannes Heikkinen; Jouni Kristian Kaukovuori |
| Embodiments provide an amplifier and a method for using and manufacturing said amplifier that incorporate an impedance matching stage, a feedback circuit, and a gain stage. The impedance matching stage is coupled to the feedback circuit wherein the feedback circuit provides a compensated second bias voltage for the impedance matching stage. The output of the impedance matching stage is used to set an input bias voltage for both the impedance matching stage and the gain stage. The output of the impedance matching stage is also used, together with the output of the gain stage, to produce an output of the amplifier. A signal reuse stage may be provided between the output of the impedance matching stage and the output of the amplifier. | ||||||
| 39 | Amplifier | US13271705 | 2011-10-12 | US20120293259A1 | 2012-11-22 | Jonne Juhani RIEKKI; Jari Johannes Heikkinen; Jouni Kristian Kaukovuori |
| A configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance stage whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a common-gate low noise amplifier stage whereby the low noise amplifier circuit operates as a common-gate low noise amplifier. The second topology includes one or more internal input impedance matching components and the first topology does not include the one or more internal input impedance matching components. | ||||||
| 40 | Switched-capacitor amplifier arrangement having a low input current | US12240274 | 2008-09-29 | US07944288B2 | 2011-05-17 | Detlef Ummelmann |
| An SC amplifier arrangement and a method for measuring an input voltage are described. | ||||||
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