| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 81 | Method and Apparatus for use in Digitally Tuning a Capacitor in an Integrated Circuit Device | EP12194187.6 | 2009-03-02 | EP2568608B1 | 2014-05-14 | Ranta, Tero Tapio |
| A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF- terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB. Each significant bit of the digital control word is coupled to corresponding and associated significant bit sub-circuits of the DTC, and thereby controls switching operation of the associated sub-circuit. DTCs are implemented using unit cells, wherein the LSB sub-circuit comprises a single unit cell. Next significant bit sub-circuits comprise x instantiations of the number of unit cells used to implement its associated and corresponding previous significant bit sub-circuit, wherein the value x is dependent upon a weighting coding used to weight the significant bit sub-circuits of the DTC. DTCs may be weighted in accordance with a binary code, thermometer code, a combination of the two, or any other convenient and useful code. In many embodiments, the unit cell comprises a plurality of stacked FETs in series with a capacitor. The unit cell may also include a plurality of gate resistors R G coupled to the gates of the stacked FETs, and a plurality of R DS resistors coupled across the drain and source of the stacked FETs. The stacked FETs improve the power handling capabilities of the DTC, allowing it meet or exceed high power handling requirements imposed by current and future communication standards. | ||||||
| 82 | Inductor | EP09180111.8 | 2009-12-21 | EP2337038B1 | 2014-03-12 | Nazarian, Alexe Levan; Tiemeijer, Lukas Frederik |
| 83 | Tunable inductive circuits for transceivers | EP12290160.6 | 2012-05-09 | EP2662870A1 | 2013-11-13 | Andrei, Cristian |
Presented is a tunable inductive circuit for a transceiver, the circuit having an effective inductance that may be varied. The circuit comprises a primary inductive element and a secondary inductive element spaced apart from the primary inductive element. The secondary inductive element is adapted to be activated/deactivated by a switch so as to modify the effective inductance of the circuit.
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| 84 | MULTI-LOOP WIRELESS POWER RECEIVE COIL | EP11767314.5 | 2011-07-26 | EP2599184A2 | 2013-06-05 | LOW, Zhen Ning; WHEATLEY, Charles E., III |
| Exemplary embodiments are directed to wireless power reception at a wireless power receiver. A receiver may include a coil comprising a plurality of loops. The receiver may further include a switching element coupled to the coil for selectively shorting at least one loop of the plurality. | ||||||
| 85 | Method and Apparatus for use in Digitally Tuning a Capacitor in an Integrated Circuit Device | EP12194187.6 | 2009-03-02 | EP2568608A1 | 2013-03-13 | Ranta, Tero Tapio |
A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF- terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB. Each significant bit of the digital control word is coupled to corresponding and associated significant bit sub-circuits of the DTC, and thereby controls switching operation of the associated sub-circuit. DTCs are implemented using unit cells, wherein the LSB sub-circuit comprises a single unit cell. Next significant bit sub-circuits comprise x instantiations of the number of unit cells used to implement its associated and corresponding previous significant bit sub-circuit, wherein the value x is dependent upon a weighting coding used to weight the significant bit sub-circuits of the DTC. DTCs may be weighted in accordance with a binary code, thermometer code, a combination of the two, or any other convenient and useful code. In many embodiments, the unit cell comprises a plurality of stacked FETs in series with a capacitor. The unit cell may also include a plurality of gate resistors RG coupled to the gates of the stacked FETs, and a plurality of RDS resistors coupled across the drain and source of the stacked FETs. The stacked FETs improve the power handling capabilities of the DTC, allowing it meet or exceed high power handling requirements imposed by current and future communication standards.
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| 86 | METHOD AND APPARATUS FOR USE IN DIGITALLY TUNING A CAPACITOR IN AN INTEGRATED CIRCUIT DEVICE | EP09715932.1 | 2009-03-02 | EP2255443B1 | 2012-11-28 | RANTA, Tero, Tapio |
| A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF- terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB. Each significant bit of the digital control word is coupled to corresponding and associated significant bit sub-circuits of the DTC, and thereby controls switching operation of the associated sub-circuit. DTCs are implemented using unit cells, wherein the LSB sub-circuit comprises a single unit cell. Next significant bit sub-circuits comprise x instantiations of the number of unit cells used to implement its associated and corresponding previous significant bit sub-circuit, wherein the value x is dependent upon a weighting coding used to weight the significant bit sub-circuits of the DTC. DTCs may be weighted in accordance with a binary code, thermometer code, a combination of the two, or any other convenient and useful code. In many embodiments, the unit cell comprises a plurality of stacked FETs in series with a capacitor. The unit cell may also include a plurality of gate resistors R G coupled to the gates of the stacked FETs, and a plurality of R DS resistors coupled across the drain and source of the stacked FETs. The stacked FETs improve the power handling capabilities of the DTC, allowing it meet or exceed high power handling requirements imposed by current and future communication standards. | ||||||
| 87 | AN INTEGRATED PLANAR VARIABLE TRANSFORMER WITH EMBEDDED MAGNETIC CORE | EP09799200.2 | 2009-12-01 | EP2370981A1 | 2011-10-05 | HARRISON, William, Lee; PHAM, Anh-vu; QUILICI, James, E.; DALMIA, Sidharth; KUBES, Steven, R. |
| The current invention provides an integrated planar transformer and electronic component that includes at least one wideband planar transformer disposed in a planar substrate, where each wideband planar transformer includes a planar substrate in a fully-cured and rigid state, a ferrite material embedded in the planar substrate, where the ferrite material is enveloped in an elastic and non-conductive material, inter-wound conductors disposed around the embedded ferrite material, where top and bottom conductors are bonded by an insulating adhesive. The top and bottom conductors are connected in an inter-connected pattern by conductive vias disposed on each side of the ferrite material and span through the layers to the conductors. The planar transformer further includes at least one center tap connected to at least one inter-wound conductor. The integrated planar transformer and electronic component further includes at least one electronic component connected to at least one terminal of the wide-band planar transformer. | ||||||
| 88 | Réglage d'un transformateur à changement de mode (balun) | EP09180773.5 | 2009-12-24 | EP2204877A1 | 2010-07-07 | Laporte, Claire; Ezzeddine, Hilal |
L'invention concerne un transformateur à changement de mode comportant : côté mode commun, un élément inductif (L1) en série avec un premier élément capacitif (C1) entre une borne (SE) d'accès de mode commun et la masse (GND) ; et côté mode différentiel, deux enroulements inductifs (L2) en série dont des premières extrémités respectives définissent des bornes (52, 53) d'accès différentiel et dont des secondes extrémités communes (55) sont connectées à la masse, des seconds éléments capacitifs (C2) étant respectivement connectés en parallèle sur les enroulements de mode différentiel.
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| 89 | VARIABLE INTEGRATED INDUCTOR | EP06792885.3 | 2006-08-18 | EP1929486B1 | 2009-04-29 | MATTSSON, Thomas |
| A variable integrated inductor is described herein which has an inductance value that can be switched between two or more values. In the preferred embodiment, the variable integrated inductor includes a multi-loop primary inductor which is electromagnetically coupled to a pair of secondary inductors. The secondary inductors are connected to one another to form a closed circuit within which the secondary inductors have a changeable topology that can be switched between a series connection and a parallel connection in order to change an inductance value which is output by the multi-loop primary inductor. In one application, the variable integrated inductor is used in a voltage controlled oscillator (VCO) which is of the type that can be used in a multi-band RF radio transceiver (e.g., wireless communication device). In other applications, the variable integrated inductor can be used in a tuned amplifier load, an impedance matching network, a digitally controlled oscillator or any other type of frequency selective LC- network. | ||||||
| 90 | PROGRAMMABLE INDUCTOR | EP07805054.9 | 2007-07-04 | EP2038902A1 | 2009-03-25 | BAHS, Bassem |
| The present invention provides a programmable integrated inductor (300) having a compact design, having a dual turn (302,304) and a parallel programmable impedance (310). In particular, the impedance value of the programmable changes, like a variable, programmable, as its range may be set to an unlimited number of values. The invention, thus, provides a wider range of programmable values without compromising space, at a constant equivalent given inductor area. | ||||||
| 91 | Planare Induktivität und Herstellungsverfahren | EP00128583.2 | 2000-12-27 | EP1113463B1 | 2008-04-23 | Ludorf, Werner, Dr. |
| 92 | PRECISION ROGOWSKI COIL AND METHOD FOR MANUFACTURING SAME | EP05852426.5 | 2005-11-30 | EP1844481A2 | 2007-10-17 | SKENDZIC, Veselin; KESLER, James, R. |
| An improved Rogowski coil is formed on a toroidal core (10) mad of a thermoplastic or other moldable material, the core having a preferably continuous groove or grooves (12) extending around the core. The grooves correspond in size to magnet wire which registers within the grooves, thus controlling the specific location of the wires. The grooving may be helical. A return loop can be provided for return path cancellation, or a reverse winding can be added in a direction opposite to the direction of advancement of the main coil. In using the return loop, a resistive network can be added to improve the cancellation of the return path due to the effect of geometries. In addition, it can compensate for thermal and other variations. | ||||||
| 93 | PLANAR INDUCTOR | EP05751618.9 | 2005-06-17 | EP1761938A1 | 2007-03-14 | TIEMEIJER, Lukas, F. |
| A planar inductor (50) comprises a conductive path in the form of a spiral pattern (53A-53D, 54A-54D). A conductive connecting path (62A, 63) connects a terminal (60) to an intermediate tap point (61A). The connecting path comprises at least one path portion which is radially directed with respect to the spiral pattern (53A-53D). The connecting path (62A, 63) can be routed via the inside of the spiral pattern. Where the connecting path comprises only radially-directed path portions, they are commonly joined at the centre (64) of the spiral pattern. Multiple path portions (62A, 62B) can each connect to the intermediate tap point of a respective conductive path. The connecting path can use a further conductive track (85) which is parallel to the conductive path which forms the spiral pattern. | ||||||
| 94 | Parallel-structured switched inductor circuit | EP06250707.4 | 2006-02-09 | EP1691480A1 | 2006-08-16 | Eo, Yun-seong; Lee, Kwang-du; Bang, Hee-mun; Lee, Heung-bae |
An inductor circuit includes a pair of inductors connected in parallel with each other and a switch for turning on and off electric power to one of the pair of inductors. The inductance of the inductor circuit can be varied and the quality factor Q can be improved. Further, RF circuits employing the inductor circuit can generate an intended operating frequency.
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| 95 | Variable inductor device | EP98402792.0 | 1998-11-10 | EP0917162B1 | 2006-02-01 | Iida, Naoki; Uchiyama, Kazuyoshi; Matsuta, Katsuji; Kawaguchi, Masahiko |
| 96 | MULTI-TAP COIL | EP03738402.1 | 2003-06-25 | EP1527462A1 | 2005-05-04 | DOLMANS, Wilhelmus, M., C.; VAUCHER, Cicero, S. |
| The invention relates to multi-band resonator circuits with inductors and capacitors. These resonator circuits are realized on integrated circuits. The inductors are realized according to the invention within one single coil comprising a center (2) tap and intermediate taps (4, 6). | ||||||
| 97 | Planare Induktivität | EP00128583.2 | 2000-12-27 | EP1113463A1 | 2001-07-04 | Ludorf, Werner, Dr. |
Eine planare Induktivität wird durch mehrere Windungen (10-12) in Form von gedruckten Leiterbahnen auf mindestens einer Trägerplatte (1) gebildet. Mehrere separate Anzapfungs-Leiterbahnen (20-22) verbinden jeweils eine Windung (10-12) mit einem gleichen Endanschluß (3) der Induktivität. Zum nachträglichen Verändern der Induktivität können Abgleich-Abschnitte (30-32) der Anzapfungs-Leiterbahnen (20-22) mittels Laserstrahlen oder Anlegen eines Stromes hoher Stromstärke durchtrennt werden. |
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| 98 | PRINTED CIRCUIT BOARD INDUCTOR | EP95931540 | 1995-08-18 | EP0782754A4 | 1998-08-19 | EBERHARDT JOHN E |
| A multilayer printed circuit board (100) includes a plurality of layers (101, 102, 104, 106, 108 and 110). Located within intermediate layer (106) is an inductor (200) which is shielded by top layer ground plane (202) and bottom layer ground plane (204). In another embodiment of the present invention, the inductor (200) can have its inductance adjusted by way of an inductance adjustement runner (316, 318) or by an electronic inductance adjustement device (408). | ||||||
| 99 | PRINTED CIRCUIT BOARD INDUCTOR | EP95931540.0 | 1995-08-18 | EP0782754A1 | 1997-07-09 | EBERHARDT, John, E. |
| A multilayer printed circuit board (100) includes a plurality of layers (101, 102, 104, 106, 108 and 110). Located within intermediate layer (106) is an inductor (200) which is shielded by top layer ground plane (202) and bottom layer ground plane (204). In another embodiment of the present invention, the inductor (200) can have its inductance adjusted by way of an inductance adjustement runner (316, 318) or by an electronic inductance adjustement device (408). | ||||||
| 100 | Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device | EP14165804.7 | 2009-03-02 | EP2760136B1 | 2018-05-09 | Ranta, Tero Tapio |
| A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF- terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB. Each significant bit of the digital control word is coupled to corresponding and associated significant bit sub-circuits of the DTC, and thereby controls switching operation of the associated sub-circuit. DTCs are implemented using unit cells, wherein the LSB sub-circuit comprises a single unit cell. Next significant bit sub-circuits comprise x instantiations of the number of unit cells used to implement its associated and corresponding previous significant bit sub-circuit, wherein the value x is dependent upon a weighting coding used to weight the significant bit sub-circuits of the DTC. DTCs may be weighted in accordance with a binary code, thermometer code, a combination of the two, or any other convenient and useful code. In many embodiments, the unit cell comprises a plurality of stacked FETs in series with a capacitor. The unit cell may also include a plurality of gate resistors R G coupled to the gates of the stacked FETs, and a plurality of R DS resistors coupled across the drain and source of the stacked FETs. The stacked FETs improve the power handling capabilities of the DTC, allowing it meet or exceed high power handling requirements imposed by current and future communication standards. | ||||||
