Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.

To improve the compressibility of data including consecutive runs of the same value.

First encoding means (1a) encodes, within the compression target data (4), each part with a sequence of the same value into the number of consecutive runs of the value. Decomposing means (1b) decomposes the number of consecutive runs of the same value into an addition of integers belonging to a predetermined integer group. Calculating means (1d) calculates the probability of occurrence of each integer obtained by the decomposition. Second encoding means (1e) encodes each integer by assigning shorter codes to integers with higher probabilities of occurrence.