子分类：
| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Alignment and ordering of vector elements for single instruction multiple data processing | US947649 | 1997-10-09 | US5933650A | 1999-08-03 | Timothy J. van Hook; Peter Hsu; William A. Huffman; Henry P. Moreton; Earl A. Killian |
| The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing. | ||||||
| 182 | Method and apparatus for processing packed data | US32764 | 1993-03-16 | US5909552A | 1999-06-01 | Allen Peter Jensen; Michael Terrell Vanover |
| A method and an apparatus for processing a plurality of operands in parallel including packing the operands into a word with at least one cleared buffer bit between each operand and processing the packed word. | ||||||
| 183 | Pipelined data processing device having improved hardware control over an arithmetic operations unit | US586483 | 1996-01-16 | US5822557A | 1998-10-13 | Seiji Suetake; Koichi Hatta; Hideyuki Iino; Tatsuya Nagasawa |
| An arithmetic operation unit for operating according to pipeline control and an instruction decoder for controlling the arithmetic operation unit by decoding an instruction, including a state retaining unit for retaining a state of the operation of the arithmetic operation unit, wherein the instruction decoder controls the execution of the arithmetic operation unit according to the information stored by the state retaining unit. A state is set when the decoder issues a signal for starting the arithmetic operation unit and the state is cleared when the decoder issues a signal for stopping the operation of the arithmetic operation unit. The arithmetic operation unit further comprises a unit for obtaining a maximum and a minimum value with a simple construction. A multiplier of the arithmetic operation unit comprises a unit for performing an addition of an exponential part of a multiplier and that of a multiplicand with a simple construction. The arithmetic operation unit further comprises a data packing and unpacking unit for packing and unpacking vector data. The data processing device is divided into several units and scan paths are divided into several paths corresponding to respective units. | ||||||
| 184 | Specialized millicode instruction for certain decimal operations | US614249 | 1996-03-12 | US5754810A | 1998-05-19 | Charles Franklin Webb; Mark Steven Farrell; Charles Lewis Cross; Nishit Hemantkumar Gokli; Wen He Li |
| A millicode method for packing the hexadecimal digits from a plurality of bytes in each of two millicode registers (R1,R1) into one of the two millicode registers extracts the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R1 and the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R2 and stores hexadecimal digits from said extracting step in millicode register R1 with each hexadecimal digit extracted from a byte in register R1 and from a byte in register R2 stored in millicode register R1 in register R1 positions occupied by said plurality of bytes stored in register R1 prior to said extraction step. | ||||||
| 185 | Adaptive 128-bit floating point load and store operations for quadruple precision compatibility | US580035 | 1995-12-20 | US5729724A | 1998-03-17 | Harshvardhan Sharangpani; Donald Alpert; Hans Mulder |
| A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s. When values are moved to memory the reverse operation is performed. | ||||||
| 186 | High speed microprocessor for processing and transferring N-bits of M-bit data | US487170 | 1995-06-07 | US5708800A | 1998-01-13 | Hiroshi Tateishi; Hiroki Takahashi; Kazuo Nakamura |
| A microprocessor comprises a control section for receiving a transfer instruction and transferring N-bits of M-bit data stored at a transfer-source address in a first memory to a transfer-destination address in a second memory in response to a received transfer instruction. In this microprocessor, the transfer of N-bits is performed with the execution of a single transfer instruction. Hence, the memory area required for storing the transfer instructions is reduced, and the residual memory area can be used for other purposes, which improves the efficiency in the use of the memory. The control section stores in the first memory of the microprocessor all the interim results obtained during the execution of a transfer instruction and outputs only the final result to the external memory, reducing the number of machine cycles required for data transfer between the microprocessor and the memory, and further reducing the execution time for data transfer in the microprocessor. | ||||||
| 187 | Method of converting data and device for performing the method | US257201 | 1994-06-09 | US5694580A | 1997-12-02 | Masahiko Narita; Akiyoshi Katsumata; Makiko Shimamura; Akiro Nagatome; Masaki Satoh |
| A data conversion apparatus includes a plurality of computers connected to a network, a storage section, a retrieval section, data conversion processing sections, and a control section. The storage section stores plural sorts of information on the converter including a name of a computer equipped with a converter, a way of using the converter. A retrieval section retrieves information on the subject converter from the storage section according to a conversion request from a computer which requesting data conversion. The data conversion processing sections are connected to the respective computers and converts data into data of a format to be used with the converter on the basis of the result retrieved by the retrieval section. The control section controls the retrieval processing of the retrieval section and the conversion processing of the data conversion processing section to output converted data to the computer which requests data conversion. | ||||||
| 188 | FIFO memory device capable of writing contiguous data into rows | US391647 | 1995-02-21 | US5521876A | 1996-05-28 | Hiroshi Hattori; Junich Sugiyama |
| A FIFO memory device includes a storage device and an address translator. The storage device contains a plurality of FIFO storage units cells connected in parallel, wherein data is input to and output from each of the FIFO storage unit cells one word at a time, and data is input to the storage device one word at a time and output from the storage device in units of a plurality of words. The address translator is disposed between a central processing unit and an input side of the storage device for translating an address specified by the central processing unit into an address specifying one of the storage unit cells of the storage device. The address translator includes a count enable signal output element responsive to addressing from the central processing unit for outputting a count enable signal, a counter responsive to the count enable signal from the count enable signal output element for counting up, and a selector responsive to a count value of the counter for selecting one of the storage unit cells. | ||||||
| 189 | Method and apparatus for converting image data between bit-plane and multi-bit pixel data formats | US96461 | 1993-07-23 | US5461680A | 1995-10-24 | Hedley Davis |
| A circuit which transforms image data between bit-plane data representations and multi-bit pixel representations includes a plurality of sequential logic elements arranged as a matrix having columns and rows. Data values representing bit-plane data are stored into the columns of the matrix according to a first scheme and data values representing multi-bit pixel data are stored into the columns of the matrix according to a second scheme. Data applied to the columns of the matrix is shifted along the rows until the matrix is filled. The converted data is then read out along the rows of the matrix. | ||||||
| 190 | Method and apparatus for initializing an ECC circuit | US974158 | 1992-11-10 | US5428627A | 1995-06-27 | Alok K. Gupta |
| A method and apparatus for converting input symbols of a fixed length, to output symbols of a greater fixed length. Input symbols are received one at a time and are clocked into the staging register. When a new input symbol is loaded into the staging register, the contents of the first stage are moved to a second stage of the staging register. The new input symbol is loaded into the cells of the first stage. Multiplexers select the contents of cells of the staging register to form the output symbol. A modulo-x counter counts the incoming input symbols. The output of the counter determines which cells the multiplexer selects. Initially, the first stage of the staging register is preloaded with a predetermined pad symbol, and the modulo-x counter is preset. The first output symbol consists of a number of bits from the pad symbol and those bits of the first input symbol needed to complete the first output symbol. | ||||||
| 191 | Apparatus for cell format control in a spread sheet | US838352 | 1992-02-19 | US5280575A | 1994-01-18 | Carol A. Young; Neal F. Jacobson |
| A data structure for tabular data arranged in rows and columns. The data structure includes a header portion including a generic columnar processing information table, and a data portion for storing data in rows, the data portion further identifying a table containing generic columnar processing information to be used in processing selected cells in the row. In a refinement, each row in the data structure includes a row header including a row number and at least one cell, the row number identifying a row in a table for the cell. As a further refinement, each cell includes a header portion and a value portion, the header portion containing a cell number identifying a column in a table for the cell. | ||||||
| 192 | Bit serial floating point parallel processing system and method | US951930 | 1992-09-25 | US5268856A | 1993-12-07 | Stephen S. Wilson |
| A system and method for floating point computations involving matrices or vectors includes a plurality of identical processing units connected to a linear chain with direct data communication links between adjacent processing units. Each such processor is also connected to its own private memory. A sequence of instructions is sent by a controller to all floating point processing units and their associated memories whereby all processing units in the chain receive the same instruction and all memories receive the same address at any given cycle in the instruction sequence. Each processing unit internally handles floating point operations such as normalization, sign changes, and multiplication in a bit serial manner. | ||||||
| 193 | Semiconductor memory device having redundancy and capable of sequentially selecting memory cell lines | US500328 | 1990-03-28 | US5053999A | 1991-10-01 | Tetsuya Matsumura; Masahiko Yoshimoto |
| First-In First-Out (FIFO) memory device is disclosed. A ring pointer circuit sequentially and repeatedly selects memory cells in a memory cell array. When it is detected that a defective memory cell exists on a memory cell row, selection of that memory cell row is invalidated by the ring pointer circuit by cutting off a laser trimming line. In addition, by selectively cutting off laser trimming lines in a switching circuit and a redundancy ring pointer circuit, a redundancy memory cell row is selectively added in place of the defective memory cell row. Accordingly, stages required for the ring pointer circuit are maintained. In other words, the FIFO memory device having a defective memory cell is saved, resulting in improvement in yield in the manufacture. | ||||||
| 194 | Method for the formatting and unformatting of data resulting from the encoding of digital information using a variable length code and a device for using this method | US2218 | 1987-01-12 | US4739308A | 1988-04-19 | Jean Lienard |
| The formatting/unformatting device of the invention especially comprises a formatting device made up of a justifier linked to an input register, the output of which is linked, through a multiplexer, to the residue input of the justifier as well as to a first intermediate register through another multiplexer and to another multiplexer. The latter multiplexer is linked to a second intermediate register and an output multiplexer, the output of which is linked to an output register which acts as a buffer for the bulk memory. | ||||||
| 195 | Serial-to-parallel and parallel-toserial buffer-converter using a core matrix | US42935665 | 1965-02-01 | US3333253A | 1967-07-25 | SAHULKA RICHARD J |
| 196 | Circuit arrangement for modifying bit sequences in accordance with certain characteristic properties thereof | US22246262 | 1962-09-10 | US3259882A | 1966-07-05 | GUNTER HOTZ |
| 197 | Byte converter | US78466959 | 1959-01-02 | US3079597A | 1963-02-26 | WILD HERBERT K |
| 198 | 情報処理装置、プログラム、情報処理方法及びデータ構造 | JP2017083747 | 2017-04-20 | JP2018181196A | 2018-11-15 | 松村 秀敏 |
| 【課題】回路規模の増大を防止することが可能な情報処理装置等を提供することを目的とする。 【解決手段】情報処理装置1は、圧縮対象の対象データを所定の演算処理により第1データへ変換する変換部と、変換した前記第1データ及び前記対象データのファイルを特定するための識別情報に基づき第2データを生成する生成部と、生成した前記第2データに対応するメモリのアドレスに前記対象データを記憶する記憶処理部とを備える。また前記生成部は、前記第1データと前記識別情報とを加算して第2データを生成する。 【選択図】図1 |
||||||
| 199 | 機械命令を実行することによってデータをある形式から別の形式に変換する方法、コンピュータ・プログラム、およびコンピュータ・システム | JP2017515731 | 2015-09-15 | JP2017531860A | 2017-10-26 | ブラッドベリー、ジョナサン、デイヴィッド; カルラフ、スティーブン; コープランド、レイド; ミトラン、マーセル |
| 【課題】機械命令を実行してデータをパック10進数形式から10進浮動小数点形式に変換するための方法を提供する。【解決手段】方法は、パック10進数形式のデータを、通信可能にプロセッサに結合されたメモリから読み取る。方法は、パック10進数形式のデータを10進浮動小数点形式に変換する。方法は、10進浮動小数点形式に変換されたデータを、プロセッサの1つまたは複数のターゲットのレジスタに書き込む。【選択図】図3 | ||||||
| 200 | 情報処理装置、十進数変換方法および十進数変換プログラム | JP2016000152 | 2016-01-04 | JP2017122951A | 2017-07-13 | 中村 実 |
| 【課題】二進数データから十進数データへの変換の計算量を削減する。 【解決手段】記憶部11は、二進表現の4ビットと十進表現の1桁との対応を示す変換情報13を記憶する。変換部12は、二進数データ14から連続する4ビットを選択し、変換情報13を参照して、二進数データ14における選択した4ビットの位置とその少なくとも一部のビットの値とから、十進数データ15の1桁の値を決定する。変換部12は、二進数データ14から決定した1桁の値に対応する二進数を減算する。変換部12は、減算後の二進数データ14から他の4ビットを選択して十進数データ15の他の1桁の値を決定することを繰り返すことで、二進数データ14を十進数データ15に変換する。 【選択図】図1 |
||||||
QQ群二维码
意见反馈
意见反馈