| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | Self-synchronization type scrambler | JP11987985 | 1985-06-04 | JPS612443A | 1986-01-08 | REGINHARUTO POSUPISHIRU |
| 162 | Information compression processing system | JP10402883 | 1983-06-09 | JPS59228419A | 1984-12-21 | DEMACHI TAMOTSU |
| PURPOSE:To transfer efficiently a parallel data by calculating a difference data between a present reception parallel data and a preceding reception parallel data so as to discriminate the significance of the data compressing processing. CONSTITUTION:A data received at this time is applied from a register A2 and a data received at a preceding time is applied from a register B3 to a difference calculator 4. The difference calculator 4 calculates the difference of those data. This calculated difference data is applied to a data selector 5 and a maximum bit number calculator 6. The maximum bit number calculator 6 transmits a signal whether the data selector 5 applied the received data to a parallel serial converter 7 as it is or the difference data from the difference calculator 4 is applied to the parallel serial converter 7 to the data selector 5. | ||||||
| 163 | JPS59166542U - | JP6136483 | 1983-04-23 | JPS59166542U | 1984-11-08 | |
| 164 | Data compressing system | JP5671583 | 1983-03-31 | JPS59182647A | 1984-10-17 | HIRAKAWA KOUJI |
| PURPOSE:To remarkably content of data and to reduce the transmission time by transmitting a data train to a compressing and converting section and obtaining a compression value from a maximum value included in the data train and a calculated value in an operating section. CONSTITUTION:An input data train ei is stored in an input data storage section 6, the data train ei is fed to the compression and converting processing section 7, and the maximum value M included in the data train ei is detected. The compressing value V is obtained by this maximum value M and the calculated value in the operating section 8, these values M, V are transmitted to an output buffer section 10 or a storage holding section 11 and transmitted to a communication line. Then, the data compressed by this compressing system is read from a file 13 via the communication line and stored in an input data storage section 14. The compressing data comprising the stored maximum value M and compressed value V is fed to a restoration processing section 15, the processing section and the operation section 16 perform restoring processing, and the restored data is stored in a data section 18. | ||||||
| 165 | JPS5853402B2 - | JP7903074 | 1974-07-10 | JPS5853402B2 | 1983-11-29 | RAMESHU ESU PATERU; DEEBITSUDO ESU DAN |
| 166 | JPS5831642B2 - | JP12316376 | 1976-10-14 | JPS5831642B2 | 1983-07-07 | KASHIO TOSHIO |
| 167 | Code converter | JP7162981 | 1981-05-13 | JPS57186861A | 1982-11-17 | OKAMOTO EIJI |
| PURPOSE:To shorten a processing time by a comparatively small scale, by constituting a code converter of a data cycling device, a selective multiplier, a remainder device and a square device. CONSTITUTION:Input data sequences a0, a1, a2, ... applied to an input terminal 101 are applied to a data cycling device 103 and are outputted cyclically only for a prescribed time. A selective multiplier 104 selectively switches to one of a data from the cycling device 103 as it is, or the product of the data of the cycling device 103 and a data of a square device 106, or the data of the square device as it is, and provides it to a remainder device 105. The remainder device 105 converts the data from the multiplier 104 to the remainder divided by a positive integer (n). Also, the square device 106 converts the data from the remainder device 105 to a data squared by making (n) a root, and provides it to the multiplier 104. As a result, the remainder obtained by dividing a0<m>, a1<m>, a2<m>, ... (m is a positive integer) by (n) is outputted to an output terminal 102. In this way, this code converter is constituted like a pipeline, therefore, its processing time is shortened to log2m or so of the processing time of the multiplier. | ||||||
| 168 | Communication controller providing code converting function | JP6311180 | 1980-05-12 | JPS56158553A | 1981-12-07 | OIKAWA MASANORI |
| PURPOSE:To simplify the constitution of character processing and to reduce the load of processors, by installing a code conversion table between a serial-parallel conversion section and a character processing section according to each communication line. CONSTITUTION:In communication controller allocating a plurality of data communication lines, code conversion sections 220-1-220-n are provided according to each communication line between serial conversion sections 210-1-210-n and a character processing section 230. Thus, if the code system in a system can adopt only the same one to all the lines, the character processing section 230 can make the character processing of sole code system. Further, if the code system of each line cannot be the same, the transmission control processing of the character processing section is made common with the information stored in the additional control field after the code conversion to reduce the load. | ||||||
| 169 | Character conversion system | JP4844380 | 1980-04-11 | JPS56144654A | 1981-11-11 | HAYAKAWA EI; EGUCHI MASATO; NUMAZAWA KAZUMI |
| PURPOSE:To reconvert output converted character B to character A while securing the continuity of the character, and to detect character A rapidly by comparing patterns of character inputted by (m) bits together at every time, by (m) bits together at every time. CONSTITUTION:An eight-bit character is inputted from input line 11 and in memory 12, on the other hand, coordinate relations among patterns A, B and C are stored. Comparator 13 makes six-bit comparisons between the both to discriminate identical pattern A (e.g. pattern A.1). Once the coincidence is discriminated as many times as prescribed, a signal is sent to control circuit 14, which discriminates pattern A (e.g. pattern A.3) detected finally by comparator 13 and then reads out of memory 12 the pattern B.5 that corresponds to pattern A.5 to follow it next. | ||||||
| 170 | Code conversion circuit | JP17255179 | 1979-12-28 | JPS5696553A | 1981-08-04 | INOUE KOUICHI; MURATA EIICHIROU; YAMANE MANABU; NAKANISHI TETSUAKI |
| PURPOSE:To realize the combination of a number of codes with a comparatively simple circuit, by using the output of an exclusive logical sum gate for the address designation of memory via a shift register and decoder. CONSTITUTION:An input signal is fed to one input of an exclusive logical sum gate 1, the output is fed to a 8-bit shift register 2, and the output of, e.g., 3 prestages of the register 2 is fed to a decoder 3. Further, the output decoded into 8 signals designates the address of a bit memory 4, and the output of the memory 4 is fed to another input of the gate 1. Thus, the combination of codes in 14336 ways can be made. | ||||||
| 171 | Pulse modulation system | JP5182679 | 1979-04-26 | JPS55143826A | 1980-11-10 | KOTSUKAWA TOSHIHIKO; MURATA TADASHI; SATOU MITSUTAKE; OONISHI RIYOUICHI; TACHIKI TAKEHIKO |
| PURPOSE:To improve a modulation efficiency by giving information to the width as well as the interval of pulses. CONSTITUTION:The output of a 2/(2, 2) converter in pulse interval and width modulator 62 becomes the preset signal of counters 81 and 82, and these counters count timing signals (e) and (f), which are distributed alternately, by the number of preset and generate end signals (g) and (h) at the count completion. These end signals are supplied to RS-FF84, and i-number on and j-number off are generated correspondingly to codes (i) and (j) to generate pulse interval and width modulation signal (k), and code read controller 83 instructs converter 2/(2, 2) to transmit the code and controls the read of counters 81 and 82 on a basis of the change point of signal (k). Meanwhile, clock generator 85 generates prescribed-period clocks, and these clocks are gated in gate circuits 86 and 88 by signal (k) and the inverted signal obtained by causing signal (k) to pass through inverter 87 and are supplied to counter 81 and 82 alternately. Consequently, information is given to the width as well as the interval of pulses, and the modulation efficiency can be improved. | ||||||
| 172 | JPS5528126B2 - | JP13215374 | 1974-11-15 | JPS5528126B2 | 1980-07-25 | |
| 173 | Code converter | JP15843578 | 1978-12-25 | JPS5586242A | 1980-06-28 | MORIYAMA KAZU; KIOGAWA TAKAO |
| PURPOSE:To make it possible to send out an output of conversion of an input Roman character input into a katakana character (Japanese syllabary) code, by providing a code converter with a character converting function between katakana characters and Roman characters. CONSTITUTION:To input characters by a five-unit code terminal equipment, a shift code, discrimination code for discriminating whether an alphabetic document is Japanese or English, and the alphabetic document or symbols are inputted in sequence following a function key. A code conveter stores the position of the shift code first and decides upon letters and numbers or symbols to extract them respectively while storing them. Next, a decision on whether letter codes are outputted as the English writing is or Roman characters are converted into katakana characters is made and after Roman characters are converted into katakana codes, six- unit codes are outputted. Those extracted letter, characters and symbols are outputted by a six-unit code terminal equipment. Further, Roman characters which can not be converted into katakana codes are outputted as they are and as to characters disagreeing with conversion rules, error codes are outputted. | ||||||
| 174 | JPS5320845B2 - | JP8899771 | 1971-11-10 | JPS5320845B2 | 1978-06-29 | |
| 175 | Error correcting method and system for facsimile transmission | JP9520877 | 1977-08-10 | JPS5337313A | 1978-04-06 | REIMON JIORUJIYU SHIYAI; PIITAA HOMAN; URUFU ROOTOGORUTO |
| 176 | Information transmission system | JP11032576 | 1976-09-14 | JPS5335404A | 1978-04-01 | OBARA YOUICHI |
| 177 | Information reading method and apparatus | JP9170676 | 1976-07-30 | JPS5317313A | 1978-02-17 | MASUDA TAKAO |
| PURPOSE: To gate information signal accurately by generating a gate signal at the ending of timer operation when a clock signal is dropped out. COPYRIGHT: (C)1978,JPO&Japio | ||||||
| 178 | Discriminating method and circuit | JP5698177 | 1977-05-17 | JPS52143006A | 1977-11-29 | MARIO MATSUZORA |
| 179 | JPS522612B2 - | JP9384872 | 1972-09-19 | JPS522612B2 | 1977-01-22 | |
| 180 | JPS523518U - | JP8794875 | 1975-06-24 | JPS523518U | 1977-01-11 | |
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