| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 141 | Encoding and decoding device and its method | JP22468698 | 1998-08-07 | JP2000059227A | 2000-02-25 | FUJIMOTO SHOICHI |
| PROBLEM TO BE SOLVED: To precisely decode a code, which is obtained by decoding such as expressing digital data by a smaller number of bits, to original digital data without deteriorating precision. SOLUTION: The continuing number of 0 is investigated from the lowest order bit of digital data 103, a value obtained by subtracting a number larger than this continuing number of 0 by one from the bit number of data 103 is set to be the number of assigned bits 105 and the bit is assigned from the highest order bit of data 103 according to this number 105. The number of bits reduced by using the number of assigned bits 114 (105) and a low-order bit which is provided with the size and where a highest-order is 1 and the other bits are 0 is generated. This low-order bit is connected to the low-order side of a code 115 (106) to decode to original digital data 117. | ||||||
| 142 | Control device for material testing machine | JP8198998 | 1998-03-27 | JPH11281553A | 1999-10-15 | WATANABE NAOTO; ISHII YUZO |
| PROBLEM TO BE SOLVED: To provide a control device, for a material testing machine, by which an item condition used to specify a test condition can be input and controlled by using a screen, interactively, simply and efficiently. SOLUTION: A setting-content screen 1 by which a plurality of item conditions used to specify a test condition are displayed by item groups which are sorted in advance according to their contents is provided. A plurality of test-condition setting screen 2 which are used to set the item conditions of the item groups are provided. A plurality of glance display screens 4 by which the set contents of the item conditions to be set by test conditions by using the test-condition setting screen 2 are glance-displayed in every item group are provided. Pieces of tab information 1a, 2a, 4a which are displayed collectively so as to be added to the respective screens 4 and which are used to change over a display between the respective screens 4 are provided. While the respective screens 4 are being changed over according to the pieces of tab information 1a, 2a, 4a, the respective item conditions are set. Their set contents are controlled by using the setting-content screen 1 and the glance display screens 4. COPYRIGHT: (C)1999,JPO | ||||||
| 143 | Processing unit and an arithmetic processing method | JP4403397 | 1997-02-27 | JP2856190B2 | 1999-02-10 | UEJIMA YOSHUKI |
| 144 | Parallel comparison type a-d converter | JP4743190 | 1990-02-28 | JP2844806B2 | 1999-01-13 | GENDAI JUJI |
| 145 | Encoding and decoding method and facsimile apparatus of image data | JP30141089 | 1989-11-20 | JP2807293B2 | 1998-10-08 | MATSUI KINEO |
| PURPOSE:To facilitate synthesis and separation of other data by utilizing the correlation with arrangement of image elements on a reference scanning line and its run length. CONSTITUTION:Each image element on a scanning line with respect to an original image is binarized and the original image is compressed depending on the 2-dimension encoding method or a linear encoding method based on the correlation between the arrangement of the binarized image elements and the arrangement of the image elements on the reference scanning line. In this case, a synthesis data superimposed on the original image is sequentially read and when the 2-dimension encoding method is adopted for compressing the original image, the condition of the correlation between the arrangement of the binarized image elements and the arrangement of the image elements on the reference scanning line is corrected based on the synthesized data, and in the case of the linear encoding method, the condition of even/odd property provided to the run length is corrected based on the synthesized data. Thus, the other data is synthesized and separated easily. | ||||||
| 146 | Arithmetic processing unit and its method | JP4403397 | 1997-02-27 | JPH10242984A | 1998-09-11 | UEJIMA YOSHIYUKI |
| PROBLEM TO BE SOLVED: To simplify a DC bias suppressing circuitry for transmitting data. SOLUTION: A 1st counter A16 for executing the operation of a whitener encoder executes up/down counting only by +3, +1, -1, or -3 in accordance with judgment whether 2-bit symbol data in an n-bit section partitioned by two n/2 bit shift registers 13a, 13b are '10', '11', '01' or '00' and a 2nd counter B17 executes up/down counting only by +3, +1, -1, or -3 in accordance with judgment whether already sent 2-bit symbol data are '10', '11', '01', or '00'. The inversion availability of transmitting data is judged by judging the most significant bit of each counter by a comparator 18. When both the code bits of the counters 16, 17 are '0' or '1', the transmitting data are inverted, and when one of two code bits is '0' and the other is '1', inversion is not executed. Each of bit stuff circuits 14a, 14b inserts one-bit data into the transmitting data in each n/2 bits. COPYRIGHT: (C)1998,JPO | ||||||
| 147 | Measurement value conversion method | JP2249085 | 1985-02-07 | JPH0766479B2 | 1995-07-19 | 久貴 伊藤 |
| 148 | Inverse quantizer | JP20514791 | 1991-08-15 | JPH0548464A | 1993-02-26 | KONO TADAMI; TANAKA ATSUSHI |
| PURPOSE:To provide the inverse quantizer whose circuit scale can be reduced. CONSTITUTION:In the inverse quantizer in which a quantized step size, an inverse quantization level and an inverse quantization weight coefficient are multiplied to obtain the inverse quantization value, a 1st selector 1 selects a quantization step size and an inverse quantization level, a 2nd selector 2 an inverse quantization weight coefficient and an intermediate arithmetic operation result, a multiplier 3 multiplies an output of the 1st selector 1 with an output of the 2nd selector 2, a register 4 saves the result of multiplication in the multiplier 3 tentatively to output the intermediate arithmetic operation result to multiply the inverse quantization level with the product between the quantization step size and the inverse quantization weight coefficient thereby obtaining the inverse quantization value. | ||||||
| 149 | Encoding system for hierarchized signal | JP3150291 | 1991-01-31 | JPH04245863A | 1992-09-02 | OTA MUTSUMI |
| PURPOSE: To improve encoding efficiency by giving a scan order generating the string of invalid data which is sufficiently long for a signal including the discontinuous point of an edge and the like in a picture signal in subband encoding. CONSTITUTION: Respective frequency bands are not separately encoded but they are sample point-scanned. The sample points in respective frequency bands have hourly or spatial positions which the signal expresses on an original signal. Down sampling circuits 200-203 and a scanner 400 are provided for scanning the sample points expressing the same position or the adjacent position on the original signal so that they can continue as much as possible. In a part excluding the velocity of the discontinuous point of the edge signal and the like, a part which hardly affects decoding picture quality continues even if encoding is executed near a zero level by scanning, and therefore encoding is efficiently encoded by a run length signal converter 610 and an encoder 320. COPYRIGHT: (C)1992,JPO&Japio | ||||||
| 150 | Encoding device | JP24321290 | 1990-09-13 | JPH04122174A | 1992-04-22 | KIMURA TOMOHIRO; ONO FUMITAKA; KINO SHIGENORI; YOSHIDA MASAYUKI |
| PURPOSE: To decide a succeeding state transition suitable for the tendency in the increase/decrease in a code degree order by providing the history of the tendency in the increase/decrease in a probability with another state by the history of the past transition so as to separate the route of the state transition. CONSTITUTION: A history management table 57 stores a state number to be transited next based on a coding symbol for each state and a context resident state generated by a context reference table 13 is revised to a succeeding state and when prediction value conversion is commanded, a prediction value with respect to a context is revised simultaneously and the history of the state transition is managed. A coder 18 receives A coding symbol outputted from a symbol converter 14 and a code degree number outputted from a probability estimate table 15 to implement coding outputs a code. Thus, a succeeding state transition destination suitable for the state is decided. COPYRIGHT: (C)1992,JPO&Japio | ||||||
| 151 | Frame synchronizing system | JP10356990 | 1990-04-19 | JPH042234A | 1992-01-07 | YOSHIDA HIROSHI |
| PURPOSE: To shorten the synchronization restoration time by revising the frame format of information to be sent depending on the synchronizing state at a reception side, adding synchronous information in the synchronizing state and increasing and sending the synchronous information to be added in the asynchronizing state. CONSTITUTION: When information to be sent is inputted to an mBnB conversion means 1, a frame pattern revising means 3 selects a frame format of transmission information according to the synchronous state of an opposite station and outputs the result to a frame format designation means 2. The frame format designation means 2 constitutes a frame pattern according to a frame format designated by a frame pattern revising means 3. The mBnB conversion means 1 adds additional information (control information, synchronous information and reception synchronization information, etc.) to the inputted transmission information according to the formed frame format and converts the code so that a marking rate is halved and the result is outputted. Thus, the restoration time from the asynchronous state till the synchronization establishment is shortened. COPYRIGHT: (C)1992,JPO&Japio | ||||||
| 152 | Parallel comparison type a-d converter | JP4743190 | 1990-02-28 | JPH03250816A | 1991-11-08 | GENDAI YUUJI |
| PURPOSE: To simplify the encoder constitution and to suppress generation of a sparkle by generating a low-order bit and also a complement bit with respect to the most significant bit at a 1st stage in the 1st stage encoder and allowing a next-stage encoder to use the most significant bit at the 1st stage and its complement bit thereby generating a high-order bit. CONSTITUTION: Outputs of comparator blocks 2A-2D are fed respectively to AND circuit blocks 13A-13D, outputs of the AND circuit blocks 13A-13D are fed respectively to 1st stage encoders 14A-14D and outputs of the encoders 14A-14D are fed to a next stage encoder 15. Then the 1st stage encoders generate a low-order bit and and generate a complement bit of the most significant bit D5 in the low-order bits, and the next stage encoder generate the high-order bits based on the complement bit and the most significant bit D5 in the low- order bits. Thus, the constitution of the encoders is simplified and the generation of a digital error (sparkle)is suppressed. COPYRIGHT: (C)1991,JPO&Japio | ||||||
| 153 | JPH0342762Y2 - | JP8882483 | 1983-06-10 | JPH0342762Y2 | 1991-09-06 | |
| 154 | JPH0118455B2 - | JP5661583 | 1983-03-31 | JPH0118455B2 | 1989-04-05 | YOSHIDA OSAMU; HATA MASAHIRO; OKAMURA HARUHIKO; YAMAGUCHI MASAKAZU |
| 155 | JPS6235190B2 - | JP13014479 | 1979-10-09 | JPS6235190B2 | 1987-07-31 | TOKUSHIGE KAZUO; EGUCHI TOSHIO |
| 156 | JPS6144428B2 - | JP6311180 | 1980-05-12 | JPS6144428B2 | 1986-10-02 | OIKAWA MASANORI |
| 157 | JPS6141061B2 - | JP9170676 | 1976-07-30 | JPS6141061B2 | 1986-09-12 | MASUDA TAKAO |
| 158 | JPS6112417B2 - | JP5274877 | 1977-05-10 | JPS6112417B2 | 1986-04-08 | RARII DONARUDO RAASEN |
| 159 | JPS618503B2 - | JP9508877 | 1977-08-10 | JPS618503B2 | 1986-03-14 | NOMOTO SHINSUKE |
| 160 | JPS617064B2 - | JP2466178 | 1978-03-03 | JPS617064B2 | 1986-03-04 | MIZUKURA SUSUMU; KOBAYASHI KAZUHIKO |
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