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序号 专利名 申请号 申请日 公开(公告)号 公开(公告)日 发明人
161 JPS58134795U - JP3143682 1982-03-08 JPS58134795U 1983-09-10
162 JPS5833513B2 - JP13792574 1974-12-02 JPS5833513B2 1983-07-20 TAMURA TATSUYA
163 JPS5825238B2 - JP13433778 1978-10-31 JPS5825238B2 1983-05-26 OOTA MINORU
164 JPS5822155Y2 - JP14717975 1975-10-29 JPS5822155Y2 1983-05-11
165 JPS5812154Y2 - JP1537379 1979-02-08 JPS5812154Y2 1983-03-08
166 JPS5810713B2 - JP6768472 1972-07-06 JPS5810713B2 1983-02-26 NAKADA YASUO
167 JPS5759986Y2 - JP61874 1973-12-29 JPS5759986Y2 1982-12-21
168 JPS5745580Y2 - JP2745873 1973-03-05 JPS5745580Y2 1982-10-07
169 Delay control circuit JP4273381 1981-03-24 JPS57157174A 1982-09-28 HORIBATA HITOSHI; MATSUURA TAKEHISA; MINAKI MASAZUMI
PURPOSE:To enable the execution of delay control without errors by a method wherein the output of a reference time counter corresponding to an original time to be delayed with an addition circuit is compared with a time data output set for executing a delay in a memory circuit and then, a data output to be executed is obtained with a control signal of a comparator circuit. CONSTITUTION:A reference time counter 1, a memory circuit 4, an address control circuit 3 thereof 4 and comparator circuit 5 are arranged and an addition circuit 7 is provided on the output side of a counter 1 in a circuit for delay control. It is so operated that the time data output of the addition circuit 7 corresponds to an original time to be delayed. The time data output of the addition circuit 7 is compared with the data output of a memory circuit 4 where a time set for executing a delay is memorized beforehand by means of a comparator circuit 5. Then, a delay executing output control signal CO generated following the comparison is applied to a time correction circuit 9 for time correction thereby ensuring a delay control of a given output.
170 JPS5730636Y2 - JP2745973 1973-03-05 JPS5730636Y2 1982-07-05
171 Master and slave clocks JP16459379 1979-12-18 JPS5687885A 1981-07-16 TOKITA MASAYUKI; SHIBAZAKI HISATOSHI
PURPOSE: To give a self correcting function to each slave clock by comparing time data from a master clock with the content of a time measuring circuit corresponding to the display time of slave clocks, and when there is a difference between them, by advancing slave clocks by a time corresponding to said difference. CONSTITUTION: The displaying part S of a slave clock is provided with an hour hand cam, a minute hand cam, etc., and outputs a signal a which resets a counter C when it displayed 12 o'clock 00min. In normal time, time data sent from a master clock M is one minute fast than the content of the counter C, and when these are compared (CM) and the difference is detected (A), a pulse is output from a pulse generating circuit P to a driving circuit D and advances the displaying part S by one minute. If the master clock M is set at the true time when the true time and the content of the counter C are different, the pulse generating circuit P generates pulses until the counter C becomes the time of the master clock M. If an updown counter is used for the counter C, correction of both forward and backward directions can be performed. COPYRIGHT: (C)1981,JPO&Japio
172 JPS5613672Y2 - JP11178575 1975-08-13 JPS5613672Y2 1981-03-30
173 JPS561595B2 - JP13516573 1973-11-30 JPS561595B2 1981-01-14
174 JPS5549271B2 - JP5377172 1972-06-01 JPS5549271B2 1980-12-11
175 JPS5551078Y2 - JP6158874 1974-06-05 JPS5551078Y2 1980-11-28
176 JPS55116294U - JP1537379 1979-02-08 JPS55116294U 1980-08-16
177 Auditory watch for the blind JP13998678 1978-11-14 JPS5566781A 1980-05-20 OOHIRA KAZUHIRO
PURPOSE: To obtain time information by hearing, by receiving and listening to current time through voice broadcasting. CONSTITUTION: If a current time broadcast in voice thourgh the radio waves of a particular frequency is received with a receiver, blind people can get time information through listening. COPYRIGHT: (C)1980,JPO&Japio
178 Time corrector JP13433778 1978-10-31 JPS5560880A 1980-05-08 OOTA MINORU
PURPOSE: To facilitate the correction of time, by stopping display by a time indicator, presetting the time and correcting the time depending on the difference from reference time. CONSTITUTION: Gates 30, 31 are opened through a switch 7 and a flip-flop 23. Other flip-flops 24, 25 are set by a registration key input detection signal which is supplied from a detection circuit 18 and passed through the gate 30. The indicator 3 of a secondary timepiece is stopped in response to the closing of other gates 43, 44. When presetting is performed through a registration key depending on the stopped display on the indicator 3, preset time is stored into a memory circuit 15 by an output generator 13 and displayed on the indicator 2 of a primary timepiece through a selector circuit 11. The display on the indicator 2 is replaced by an indication based on a time circuit 10 through the output generator 13 depending (result of) on the operation of an execution key. At that time, the result of time measurement by the time circuit 10 is stored into another memory circuit 16. The stored contents of the memory circuits 15, 16 are compared with each other to detect delay or gaining. The display on the indicator 3 is corrected through a calculation circuit depending on the delay or gaining. Time can thus be corrected by easy operation. COPYRIGHT: (C)1980,JPO&Japio
179 Clock device JP12130678 1978-10-02 JPS5548680A 1980-04-07 SHIYU HOUFUKU
180 JPS5515104Y2 - JP7861575 1975-06-09 JPS5515104Y2 1980-04-07
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