Delay control circuit |
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| 申请号 | JP4273381 | 申请日 | 1981-03-24 | 公开(公告)号 | JPS57157174A | 公开(公告)日 | 1982-09-28 |
| 申请人 | Mitsubishi Electric Corp; | 发明人 | HORIBATA HITOSHI; MATSUURA TAKEHISA; MINAKI MASAZUMI; | ||||
| 摘要 | PURPOSE:To enable the execution of delay control without errors by a method wherein the output of a reference time counter corresponding to an original time to be delayed with an addition circuit is compared with a time data output set for executing a delay in a memory circuit and then, a data output to be executed is obtained with a control signal of a comparator circuit. CONSTITUTION:A reference time counter 1, a memory circuit 4, an address control circuit 3 thereof 4 and comparator circuit 5 are arranged and an addition circuit 7 is provided on the output side of a counter 1 in a circuit for delay control. It is so operated that the time data output of the addition circuit 7 corresponds to an original time to be delayed. The time data output of the addition circuit 7 is compared with the data output of a memory circuit 4 where a time set for executing a delay is memorized beforehand by means of a comparator circuit 5. Then, a delay executing output control signal CO generated following the comparison is applied to a time correction circuit 9 for time correction thereby ensuring a delay control of a given output. | ||||||
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| 说明书全文 | |||||||
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