This application claims priority under 35 USC § 119(e)(1) of provisional application Ser. No. 60/214,102, filed Jun. 26, 2000.

TECHNICAL FIELD

The present invention relates generally to electrical circuits, and more particularly to a circuit and method of generating a hysteretic controller circuit having improved power efficiency at low load currents by making the natural frequency associated therewith a function of the circuit load current.

BACKGROUND OF THE INVENTION

Switching power supply circuits are utilized in a number of different circuit applications. The three basic switching power supply topologies in common use are the buck, boost and buck-boost type power stages. These topologies are non-isolated, that is, the input and output voltages share a common ground. There are, however, isolated derivations of these non-isolated topologies. The differing topologies refer to how the switches, output inductor and output capacitor associated therewith are interconnected. Each topology has unique properties which include the steady-state voltage conversion ratios, the nature of the input and output currents, and the character of the output voltage ripple. Another important property is the frequency response of the duty cycle-to-output voltage transfer function.

The most common power stage topology is the buck power stage, sometimes called a buck converter or a step-down power stage (because the output is always less than the input). The input current for a buck power stage is said to be discontinuous or pulsating if a switching current pulses from zero or some negative value to some positive output current value every switching cycle. The output current for a buck power stage is said to be continuous or nonpulsating because the output current is supplied by an output inductor/capacitor combination. In the latter event, the inductor current never reaches a zero or negative value.

An exemplary basic buck converter circuit is illustrated in prior art

FIG. 1

a

, and designated at reference numeral

10

. When a power switch

12

is activated, the switch behaves like a closed circuit, as illustrated in prior art

FIG. 1

b

, and the input voltage V

IN

is applied to an inductor

14

, and power is delivered to an output load

16

. The output load voltage is V

OUT

=V

IN

−V

L

, wherein the V

L

, the voltage across the inductor

14

, is given by L(di/dt). The output voltage V

OUT

also is formed across a capacitor

18

, thus the capacitor charges and the output voltage increases each time the switch

12

is closed.

When the switch

12

is deactivated, or turned off, the switch

12

behaves as an open circuit, as illustrated in prior art

FIG. 1

c

, and the voltage across the inductor

14

reverses due to inductive flyback, thus making a circuit diode

20

forward biased. The circuit loop generated by the diode

20

allows the energy stored in the inductor

14

to be delivered to the output load

16

, wherein the output current is smoothed by the capacitor

18

. Typical waveforms for a buck converter are shown in FIG.

2

. The power switch

12

is switched at a relatively high frequency (e.g., between about 20 KHz and about 300 KHz for most converters) to produce a chopped output voltage, however, the inductor

14

and capacitor

18

together operate as an LC filter to produce a relatively smooth output voltage having a DC component with a small ripple voltage overlying the DC value (see, e.g., output voltage waveform of FIG.

2

). The ripple voltage can be controlled by varying the duty cycle of the power switch control voltage.

The base principle of operation in the above buck converter

10

is often utilized in hysteretic dc—dc converters, as illustrated in prior art

FIG. 3

, and designated at reference numeral

30

. The circuit

30

is similar in various respects to the buck converter

10

of

FIG. 1

a

and employs a unity gain buffer

32

serially coupled to an analog comparator circuit

34

having a hysteresis V

H

. The comparator

34

compares the input reference voltage V

REF

to the circuit output voltage V

OUT

and provides an output signal at node

36

which is a function of the comparison and constitutes a generally square wave. An exemplary output voltage waveform for the circuit

30

is illustrated in FIG.

4

.

The hysteresis V

H

of the comparator

34

impacts the operation of the circuit

30

in the following manner. As the output V

OUT

falls below a voltage V

REF

−V

H

, the comparator

34

trips and the output thereof at node

36

goes from zero to the supply, ideally, which then is fed to the circuit output V

OUT

(wherein, V

OUT

is a function of the output of the comparator and the duty cycle of the driver). Similarly, as V

OUT

increases to a voltage V

OUT

+V

H

, the comparator

34

again trips and the output thereof at node

36

decreases to zero volts, which is fed to the circuit output V

OUT

. Therefore the hysteresis V

H

of the comparator

34

dictates an amount of voltage ripple (2*V

H

) about the target reference voltage V

REF

, as illustrated in

FIG. 4

, and, in conjunction with the output capacitor dictates a natural frequency of the ripple voltage at the output V

OUT

.

In many applications it is desirable to increase the natural frequency of the circuit

30

since a higher frequency allows use of a smaller capacitor, provides a smaller output ripple voltage, and provides a faster circuit response time. One conventional way of decreasing the natural frequency of a hysteretic dc—dc converter is to decrease the hysteretic window of the comparator

34

. That is, instead of using a hysteretic value of V

H

, a smaller value (e.g., V

H

−&Dgr;V

H

) is used. With a smaller hysteretic window, the comparator

34

trips earlier, thus increasing the natural frequency. While decreasing the hysteretic window in systems employing relatively large ripple voltages (e.g., on the order of about 100 mV or more) is a viable solution, such an approach is not practical in systems employing smaller ripple voltages (e.g., on the order of about 50 mV or less) because in such systems it becomes difficult to generate a well-controlled hysteresis window that is small and simultaneously insensitive to noise and random offset voltages. In other words, the accuracy requirements of the hysteretic comparator are generally more stringent for lower ripple voltages.

Therefore there is a need in the art for a circuit and method of providing an increased natural frequency in hysteretic circuits without altering the hysteretic window associated therewith.

SUMMARY OF THE INVENTION

According to the present invention, a circuit and method of altering the natural frequency of a hysteretic circuit as a function of load current is disclosed.

The present invention varies the natural frequency of a hysteretic dc—dc converter circuit as a function of the converter load current. The present invention generates and couples an AC ramp signal to the input reference voltage. The AC ramp signal preferably is an inverted version of the feedback output voltage used as the sense node in conventional circuit. The AC ramp signal has a slope which is a function of the circuit load current and is used to vary a natural frequency of the converter circuit as a function of the converter circuit load current. For example, the slope of the ramp signal is decreased as the load current decreases. The decreased ramp signal slope decreases the trip frequency of a comparator circuit which decreases the natural frequency of the converter circuit, thereby lowering switching losses associated therewith and improving the power efficiency at low load currents.

According to one aspect of the present invention, a hysteretic dc—dc converter circuit includes a feedback circuit in addition to the traditional feedback for altering a natural frequency of the converter. The feedback circuit includes positive and negative ramp current source circuits which are utilized to charge and discharge a ramp capacitor at rates which are a function of the load current. The ramp capacitor voltage is then used as the ramp signal to alter a trip frequency of a comparator circuit within the converter which results in an adjustment of the natural frequency of the converter circuit with variations in load current. For example, the positive and negative ramp current sources decrease the rate of charge and discharge of the ramp capacitor, respectively, as the load current decreases, thereby decreasing the positive and negative slopes of the ramp signal. Such decreased slopes decreases the natural frequency of the converter circuit at low load currents, thereby improving power efficiency thereat.

According to another aspect of the present invention, a method of improving the power efficiency of a hysteretic dc—dc converter is disclosed. The method comprises initiating the operation of a buck converter circuit and monitoring a load current thereof. A feedback ramp signal is then generated having a slope which is a function of the load current and the feedback ramp signal is fed to the comparator circuit. In addition, the feedback ramp signal contains the converter circuit duty cycle information. The comparator circuit then generates an output signal based on the converter output signal and the generated feedback ramp signal, wherein the comparator circuit output signal exhibits a trip frequency which is a function of the load current. In particular, the trip frequency, which is related to the natural frequency of the circuit, decreases as the load current decreases, thereby reducing switching losses at low load currents.

To the accomplishment of the foregoing and related ends, the invention, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such embodiments and their equivalents. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

a

is a circuit schematic diagram illustrating a conventional buck converter circuit which receives an input voltage signal and provides an output signal associated therewith;

FIG. 1

b

is a circuit schematic diagram illustrating the conventional buck converter of

FIG. 1

a

in an operational state where the driver or power switch is activated and behaving as a short circuit;

FIG. 1

c

is a circuit schematic diagram illustrating the conventional buck converter of

FIG. 1

a

in an operational state where the driver or power switch is not activated and behaving as an open circuit;

FIG. 2

is a series of waveform diagrams illustrating exemplary voltage and current waveforms at various nodes in the buck converter circuit of

FIG. 1

a

over a period of time as the buck converter circuit progresses through a series of differing operational states;

FIG. 3

is a circuit schematic diagram illustrating a conventional hysteretic dc—dc converter;

FIG. 4

is a waveform diagram illustrating the output voltage of the conventional hysteretic dc—dc converter of FIG.

3

and how the ripple voltage and the natural frequency associated therewith is a function of the hysteretic window of the comparator;

FIG. 5

is a waveform diagram illustrating a disadvantageous feature of prior art converter circuits, wherein the power efficiency decreases at low load currents;

FIG. 6

is a circuit schematic diagram illustrating a hysteretic dc—dc converter containing a feedback circuit for altering the natural frequency of the converter according to the present invention;

FIG. 7

is a waveform diagram illustrating circuit waveforms at various nodes of the hysteretic converter of

FIG. 6

according to the present invention;

FIG. 8

is a circuit schematic diagram illustrating a hysteretic dc—dc converter containing a feedback circuit for altering the natural frequency of the converter as a function of the load current according to the present invention;

FIG. 9

is a waveform diagram illustrating an improved power efficiency over variations in load current according to the present invention;

FIG. 10

is a circuit schematic diagram illustrating in greater detail the converter circuit of

FIG. 8

according to an exemplary aspect of the present invention;

FIG. 11

is a waveform diagram illustrating a ramp voltage waveform in the feedback circuit of

FIG. 10

according to the present invention;

FIG. 12

is a circuit schematic diagram illustrating an exemplary positive ramp current source circuit for providing a charging current which is a function of the load current according to the present invention;

FIGS. 13 and 14

are circuit schematic diagrams illustrating current source circuits according to an exemplary aspect of the present invention;

FIG. 15

is a flow chart diagram illustrating a method of altering a natural frequency of a hysteretic dc—dc converter based on the load current according to the present invention; and

FIG. 16

is a flow chart diagram illustrating a method of adjusting the natural frequency of the converter circuit based on the load current.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with respect to the accompanying drawings in which like numbered elements represent like parts.

Another problem associated with prior art dc—dc converter circuits which was appreciated by the inventor of the present invention is poor power efficiency. That is, at low load currents, the power efficiency of dc—dc converters decreases. This undesirable circuit characteristic is illustrated in prior art FIG.

5

and designated at reference numeral

95

. Note that as the load current decreases, the power efficiency falls off; this characteristic results because switching losses are constant with respect to the load current. The power efficiency of a prior art dc—dc converter circuit may be characterized by the following equation:

Power Efficiency=P

OUT

/(P

OUT

+P

CONTROL(DC)+P

CONTROL(AC)

).

As the load current decreases, P

OUT

and P

CONTROL(DC)

decreases, but the switching losses P

CONTROL(AC)

are constant because the natural frequency of prior art dc—dc converters vary minimally. The present invention overcomes the disadvantages of the prior art by varying the natural frequency of the dc—dc converter as a function of the load current. Therefore as the load current decreases, the system and method of the present invention decrease the natural frequency of the converter and thus reduce the switching losses associated therewith, thus substantially improving the power efficiency of dc—dc converters over variations in load current. Therefore the present invention makes the frequency a linear function of the load current.

The present invention is directed to a system and method of improving power efficiency in converter circuits. Such power efficiency improvements are achieved by varying the natural frequency of the converter circuit as a function of load current. In particular, as the load current decreases, the natural frequency of the converter circuit is decreased, thereby reducing the switching losses associated therewith and improving the power efficiency.

According to one particular aspect of the present invention, a circuit and method of adjusting a natural frequency of a hysteretic dc—dc converter as a function of load current without requiring an alteration of a hysteretic window associated therewith is disclosed. The invention adjusts the natural frequency of the converter by providing an additional feedback path back to the comparator. The additional feedback comprises a ramp signal which is related to the comparator output and which is out of phase therewith. The additional feedback along with an output sense node feedback increases a trip frequency of a comparator within the converter, thereby increasing a natural frequency of the converter. In addition, the slope of the ramp signal is a function of the load current, and therefore results in a variation in the natural frequency of the circuit as a function of load current. This characteristic is exploited so as to decrease the natural frequency of the circuit at low load currents and thus improve the power efficiency associated therewith.

Turning now to the figures,

FIG. 6

is an exemplary circuit schematic diagram illustrating a low ripple, high frequency hysteretic dc—dc converter circuit

100

according to the present invention. The circuit

100

includes a buffer

102

, such as a unity gain amplifier as shown, which feeds one input of a comparator circuit

104

having a hysteresis characteristic of V

H

. A feedback circuit

106

is coupled to an output of the comparator

104

and provides a feedback signal V

RAMP

back to the buffer

102

. The buffer

102

receives two input signals at its input node (V

REF′

) and thus V

REF′

=V

REF

+V

RAMP

, wherein V

REF

is an input reference voltage and V

RAMP

is a signal superimposed over V

REF

which will be discussed in greater detail below.

The output of the comparator circuit

104

is also coupled to a driver circuit

108

, such as a power switch (e.g., a BJT or a MOSFET). The driver circuit

108

is also coupled to an LC filter

112

comprising an inductor

114

and a capacitor

116

, respectively. The circuit output V

OUT

is taken across the capacitor

116

, as shown in

FIG. 5

, and is also fed back to another comparator input as a sense node

117

.

In operation, the circuit

100

provides for an increased natural frequency over conventional circuits without requiring a modification of the comparator hysteresis to alter the hysteresis window (e.g., 2*V

H

). The circuit

100

accomplishes the above operation by employing two forms of feedback to the comparator circuit

104

. In particular, the output signal V

OUT

is fed back (sense node

117

) to one terminal of the comparator in a conventional manner while another signal V

REF′

, which is out of phase with V

OUT

, is supplied to the other comparator input. Since the comparator input signals (V

REF′

and V

OUT

) are out of phase the hysteresis trip point V

H

is reached causing the comparator circuit

104

to trip although neither input signal has reached a value of V

REF

±V

H

(which was necessary to trip the comparator in prior art circuits). Therefore the natural frequency of the circuit

100

, as dictated by the frequency at which the comparator circuit

104

trips (f

2

), is increased over conventional circuits (f

2

>f

1

) although the hysteresis of the comparator (which defines the hysteresis window) is not required to be decreased.

The manner in which the circuit

100

of

FIG. 6

operates to achieve the above advantageous functionality may be further understood in conjunction with FIG.

7

. As discussed previously, the comparator circuit

104

trips when the difference between the two input terminals exceeds the hysteresis value V

H

. The manner in which the comparator circuit

104

trips (e.g., begins increasing or decreasing in a generally linear manner at its output) depends upon which of the input terminals is greater than the other. In conventional circuits (e.g., circuit

30

of FIG.

3

), the positive input terminal of the comparator was fixed while the negative input terminal (the sense node

117

) varied. Therefore the voltage swing previously necessary at the negative input terminal of the comparator to trip from one operating condition to another was 2*V

H

(e.g., from V

REF

−V

H

to V

REF

+V

H

, or vice-versa). Consequently, the hysteresis window (2*V

H

) of the comparator dictated the natural frequency in conventional circuits.

The circuit

100

of the present invention feeds back the output voltage V

OUT

to one input terminal of the comparator

104

and, instead of providing a fixed input voltage at the other comparator input terminal (as in conventional circuits), provides a varying voltage (V

REF′

) thereat which is out of phase with V

OUT

. As a result, the voltage swing at the output V

OUT

does not dictate alone the trip frequency of the comparator

104

, but instead the trip frequency is a function of both inputs. In addition, as will be described in greater detail later, the feedback voltage V

RAMP

provided by the feedback circuit

106

preferably is generated as an inverted version of V

OUT

to maximize the above-described benefit. Furthermore, the speed or slope of the ramp may be tuned to fit a variety of performance criteria, as may be desired. In particular, as will be described in greater detail infra, the slope of the ramp signal V

RAMP

is made a function of the load current such that as the load current decreases, the slope of V

RAMP

also decreases, thereby decreasing the natural frequency of the converter circuit

100

.

Referring to

FIG. 7

, exemplary voltage waveforms that are input to the comparator circuit

104

are illustrated, that is, V

REF

′ and V

OUT

, respectively. According to the present example, the two signals are 180 degrees out of phase with one another such that as one signal is increasing, the other is decreasing. As illustrated in

FIG. 7

, at point

120

, for example, the difference between the two signals is V

H

, consequently the comparator circuit

104

trips. The output of the comparator

104

is delivered to the driver circuit

108

and is also coupled to the feedback circuit

106

which uses the signal to generate V

RAMP

which, when superimposed over V

REF

provides V

REF

′ as illustrated in FIG.

7

. According to a preferred aspect of the present invention, V

RAMP

is related to the duty cycle of the driver circuit

108

and contains therein duty cycle information so that the feedback circuit

106

does not affect adversely the circuit output voltage (since V

OUT

=V

IN

*D, wherein D is the duty cycle of the drive

108

). In addition, any circuit or method of generating a feedback signal that out of phase with the output V

OUT

as discussed above may be utilized as the feedback circuit

106

and is contemplated as falling within the scope of the present invention.

A hysteretic dc—dc converter circuit employing a particular exemplary feedback circuit for generating feedback in accordance with the circuit of

FIG. 6

is illustrated in FIG.

8

. In

FIG. 8

, the feedback circuit

106

receives the output of the comparator circuit

180

(such as comparator

104

of

FIG. 6

) and a signal

190

which is representative of the load current I

LOAD

at the output V

OUT

. Using the load current signal

190

, the feedback circuit

106

generates a ramp signal V

RAMP

having a slope which is a function of the load current I

LOAD

. As discussed above in conjunction with

FIG. 7

, as the slope of V

RAMP

is altered, the trip frequency of the comparator circuit

180

changes accordingly. In particular, as the slope of V

RAMP

decreases, the trip frequency of the comparator circuit

180

decreases, thereby resulting in a decrease in the natural frequency of the circuit

175

. Since the natural frequency of the circuit

175

decreases the switching losses associated therewith also decreases (P

CONTROL(AC)

), thus improving the power efficiency at low load currents, as illustrated in FIG.

9

and designated at reference numeral

195

.

The circuit

175

of

FIG. 8

is illustrated according to one exemplary aspect of the invention in greater detail in FIG.

10

. The circuit

175

of

FIG. 10

includes a current limited CMOS inverter

202

coupled to an output of the comparator

104

. The inverter circuit

202

has a PMOS transistor

204

coupled to a positive ramp current source

206

and an NMOS transistor

208

coupled to a negative ramp current source

210

. When the output of the comparator

104

is low, the PMOS transistor

204

is on and a current dictated by the positive ramp current source

206

charges a ramp capacitor C

R

, thus causing the ramp voltage V

RAMP

to increase. Similarly, when the output of the comparator circuit

104

goes high, the NMOS transistor

208

turns on and a current dictated by the negative ramp current source

210

discharges the ramp capacitor C

R

. Such discharging causes the ramp voltage V

RAMP

to decrease.

As can be seen from

FIG. 10

, the ramp voltage V

RAMP

increases and decreases based on the output of the comparator circuit

104

. Further, the rate at which V

RAMP

changes is based on the positive ramp and negative ramp current sources

206

and

210

, respectively. According to one aspect of the present invention, the current magnitudes of the current sources

206

and

210

are a function of the load current and duty cycle, thereby making the rate at which the ramp capacitor C

R

charges and discharges a function of the load current I

LOAD

. Therefore, since I=C(dv/dt), the ramp voltage V

RAMP

is also a function of the load current I

LOAD

, as illustrated in FIG.

11

. Consequently, as the slope of V

RAMP

is changed, the trip frequency of the comparator circuit

104

is also adjusted, thereby altering the natural frequency of the converter circuit

175

.

Various circuits may be utilized for generating current sources which provide a current which is a function of the load current I

LOAD

, and any such circuit may be employed and is contemplated as falling within the scope of the present invention. One exemplary circuit for providing such functionality is illustrated in

FIG. 12

, and designated at reference numeral

250

. The circuit

250

includes a bipolar differential pair Q

1

and Q

2

having a sense resistor R

SENSE

coupled between their respective base terminals. The circuit

250

also includes two PMOS transistor M

1

and M

2

which conduct a current therethrough based on the differential voltage across the differential input pair Q

1

and Q

2

. A current source

252

is coupled in parallel with PMOS transistor M

2

.

The circuit

250

of

FIG. 12

operates as follows. The load current I

LOAD

conducts through the sense resistor R

SENSE

, thereby generating a differential input voltage across the differential input pair Q

1

and Q

2

, which is a function of the load current. That is:

V

DIFF

=I

LOAD

* R

SENSE

.

The differential pair Q

1

and Q

2

and the PMOS transistors M

1

and M

2

act as a transconductance amplifier, such that the current &Dgr;I is a function of the circuit transconductance g

m

and the differential voltage. That is:

&Dgr;

I=V

DIFF

* g

m

.

The transconductance of the circuit is one-half the tail current 2*IA divided by the thermal voltage V

T

. That is:

g

m

=½(2

*I

A

)/

V

T

=I

A

/V

T

.

Therefore &Dgr;I can be calculated in terms of the load current as follows:

&Dgr;I=V

DIFF

*g

m

=(

I

LOAD

*R

SENSE

)*(

I

A

/V

T

).

Since

I

RP

=I

A

+&Dgr;I, I

RP

can be characterized as follows:

I

RP

=I

A

+&Dgr;I=I

A

+I

A

(

I

LOAD

*R

SENSE

)/

V

T

=I

A

(1

+I

LOAD

*R

SENSE

/V

T

).

Therefore the positive ramp current I

RP

is clearly a function of the load current I

LOAD

so that as I

LOAD

decreases, I

RP

also decreases, thereby slowing the rate at which the ramp capacitor is charged.

The current source

252

of

FIG. 12

which produces I

A

may be any type of circuit which produces the above-described functionality and any such circuit is contemplated as falling within the scope of the present invention. One exemplary circuit for generating the current I

A

is illustrated in

FIG. 13

, and designated at reference numeral

260

. The circuit

260

of

FIG. 13

includes a transconductance amplifier

262

having an output which drives an NMOS transistor

264

. The source of the transistor

264

is fed back to the inverting input of the amplifier

262

and the reference voltage V

REF

is tied to the non-inverting input, respectively. Therefore the current I

A

conducting through the circuit

260

is as follows:

I

A

=(

V

REF

−0)/

R=V

REF

/R,

which is equal to V

OUT

/R since V

OUT

is approximately equal to V

REF

. Thus the magnitude of I

A

may be easily set by the magnitude of the resistor R.

The negative ramp current source

210

(I

RN

) of

FIG. 10

may be generated using a circuit which is similar to the circuit

250

of FIG.

12

. Such a circuit may differ slightly, for example, having a PNP bipolar differential input pair and a pair of gate-coupled NMOS transistors positioned below and coupled to the differential pair. The tail current source (2*I

AC

) would be positioned above the differential input pair and the &Dgr;I would be taken at the drain of one of the NMOS transistors. Of course, other circuits may also be utilized and are contemplated as falling within the scope of the present invention.

An exemplary I

AC

current source circuit for the negative ramp current source

210

(I

RN

) is illustrated in FIG.

14

and designated at reference numeral

270

. The circuit

270

includes a transconductance amplifier

272

having an output which drives a PMOS transistor

274

. The source of the PMOS transistor feeds back to an inverting input of the amplifier

272

while the reference voltage V

REF

is tied to the non-inverting input, respectively. In the above configuration, a current I

AC

is given by:

I

AC

=(

V

IN

−V

REF

)/

R

Since V

REF

is equivalent to V

OUT

, the above equation can be rewritten as:

I

AC

=(

V

IN

−V

OUT

)/

R.

Therefore the current I

AC

can be determined by the value of the resistor R and also contains the duty cycle information of the drive circuit

108

for proper operation, as may be desired. Duty cycle information is maintained as can be seen from the equations below:

The charging ramp current is:

I

CH

=I

A

=C

R

(

dv/dt

)=

C

R

(

dv/T

OFF

),

and the discharging ramp current is:

I

DIS

=I

AC

=C

R

(

dv/dt

)=

C

R

(

dv/T

ON

).

Therefore T

ON

and T

OFF

may be characterized as follows:

T

OFF

=(

C

R

/I

A

)

dv,

and

T

ON

=(

C

R

/I

AC

)

dv.

The duty cycle (D) of the converter is defined by:

D=T

ON

/(

T

ON

+T

OFF

),

therefore D can be expressed in term of the equations above as:

D=

(

C

R

/I

AC

)

dv

/[(

C

R

/I

AC

)

dv

+(

C

R

/I

A

)

dv].

By simplifying terms, the duty cycle (D) can be expressed as follows:

D=

1/[

I

AC

(1

/I

AC

+1

/I

A

)].

As shown by the equations provided supra, we know that:

I

A

=V

OUT

/R,

and

I

AC

=(

V

IN

−V

OUT

)/

R.

Therefore we can insert these equations to further solve for the duty cycle:

D=R

/[(

V

IN

−V

OUT

)(

R

/(

V

IN

−V

OUT

)+

R/V

OUT

)],

which simplifies to:

D=V

OUT

/V

IN

.

As shown above, the present invention is directed to a circuit for improving the power efficiency of a dc—dc converter circuit by varying the natural frequency of the circuit as a function of the load current. In particular, at low load currents, the natural frequency of the circuit is decreased which reduces the negative impact of switching losses associated therewith.

According to another aspect of the present invention, a method of reducing switching losses at low load currents is disclosed which increases the power efficiency of a converter circuit. Such a method is illustrated in

FIG. 15

, and designated at reference numeral

300

. The method

300

begins at step

302

by monitoring a load current of the converter circuit. The method

300

then continues at step

304

by adjusting a natural frequency of the converter circuit based on the monitored load current of step

302

. In particular, the natural frequency of the converter circuit is decreased as the load current decreases, thereby reducing switching losses associated therewith which improves the power efficiency over variations in load current.

The step

304

of adjusting the natural frequency of the converter circuit based on the load current may be accomplished in a variety of different ways and any manner of making such an adjustment is contemplated as falling within the scope of the present invention. On exemplary way of adjusting the natural frequency is illustrated in

FIG. 16. A

feedback ramp signal is generated and is fed back to the comparator circuit in a converter circuit so as to alter the trip frequency of the comparator circuit at step

306

. The slope of the generated ramp signal is then modified at step

308

based on the load current. The modified ramp signal is then fed back to the comparator circuit at step

310

to alter the trip frequency thereof, and thereby alter the natural frequency of the converter circuit. For example, the slope of the ramp signal is reduced when the load current decreases to thereby reduce the trip frequency and thus the natural frequency of the converter circuit. Therefore the natural frequency of the converter circuit decreases at low load currents which results in reduced switching losses and improved power efficiency over variations in load current.

Although the invention has been shown and described with respect to a certain preferred embodiment or embodiments, it is obvious that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of the other embodiments as may be desired and advantageous for any given or particular application.