Digital harmonic rejecting phase detector专利检索-正弦波滤波器变压器和转换设备专利检索查询-专利查询网

Digital harmonic rejecting phase detector

阅读：519发布：2023-05-15

专利汇可以提供Digital harmonic rejecting phase detector专利检索，专利查询，专利分析的服务。并且A digital harmonic rejecting phase detector inherently capable of rejecting substantially any even harmonic and with provisions for good rejection of at least one odd harmonic present in the input signal. The detector has a bidirectional counter system with a first half unidirectional counter and a second half unidirectional counter with transfer gating periodically transferring content of the first half counter to the second half counter. The bidirectional counter system accomplishes both an invert-noninvert function and the averaging function of a lowpass filter. The input signal is processed through a signal conditioner to a pulse density representation. A reference divider is provided developing the fundamental reference frequency fr and developing required odd harmonic reference frequencies (i.e., 3fr and 5fr) in square wave form. The detector processes the input signal with a VCO for a sine-wave input or a frequency multiplier for an FM input and includes a multiphase clock generator, at least one clock divider (one for each odd harmonic provided for), clock and counter controls, complement gating and two detection counters. Within the detector an increment of resolution is added or subtracted by either or''ing a pulse into the clock stream or by inhibiting a pulse from the clock stream in an operational approach eliminating any requirement for separate harmonic detectors. A small amount of additional gating implements the action of an odd harmonic detector along with gating already present for the fundamental detector.，下面是Digital harmonic rejecting phase detector专利的具体信息内容。

权利要求

1. A digital harmonic rejecting phase detector comprising: a pulse density modulated signal source producing a signal having a center frequency, a reference frequency source developing a square wave reference frequency fr and at least the first odd harmonic reference frequency 3fr, said center frequency being a multiple of said reference frequency, signal pulse splitting means dividing said signal from said pulse density modulated signal source into at least a first phase section, a second phase section, and a final phase section, clock control gating means, means connecting said reference frequency fr and said odd harmonic reference frequency to said clock control gating means, means connecting said first phase section to said clock control gating means, means including a divided by 3 divider circuit connecting said second phase section to said clock control gating means, counter means including a bidirectional counter section capable of counting an up count modulo and a down count modulo for up/down count control, and counter control circuit means interconnected with said reference frequency source, said clock control gating means, and said signal pulse splitting means for generating a clock pulse stream for application to said bidirectional counter section and including means for gate or''ing pulses into said clock pulse stream, means for gate inhibiting pulses from said clock pulse stream, and means for receiving an output from said counter means and establishing phase error and sign thereof.

2. The digital harmonic rejecting phase detector of claim 1, wherein said bidirectional counter section includes, first half counter means and a second half counter means; complement signal transfer gating means interconnecting said first and second half counter means; said reference signal fr being a square wave symmetrical signal with a first up count half cycle and a second down count half cycle connected for controlled up count by said first half counter during the up count half cycle of the fr signal; substantially instantaneous complement gate means transfer of first half counter count to said second half counter means at the initiation of the second down count half cycle of the fr signal; down count by said second half down counter during the down count half cycle of the fr signal; and counter output circuit means gate activated by the start of the next successive first up count half cycle.

3. The digital harmonic rejecting phase detector of claim 2, wherein fifth harmonic rejecting means are included with the reference frequency source also developing a second odd harmonic reference frequency 5fr square wave signal; said signal pulse splitting means also includes a third signal phase section output passed as an input to a Divided by 5 divider circuit output connected to said clock control gating means.

4. The digital harmonic rejecting phase detector of claim 2, wherein said pulse density modulated signal source includes a voltage controlled oscillator developing a relatively high frequency pulse output connectable for receiving a relatively low frequency sine wave modulating input signal.

5. The digital harmonic rejecting phase detector of claim 4, wherein the reference frequency signal fr is at substantially the same frequency as the relatively low frequency sine wave modulating input signal.

6. The digital harmonic rejecting phase detector of claim 2, wherein said pulse density modulated signal source includes a frequency multiplier circuit connectable for receiving a frequency modulated input signal.

7. The digital harmonic rejecting phase detector of claim 2, wherein sign information is extracted from the phase differential number determined and readout is made only from said second half counter.

8. The digital harmonic rejecting phase detector of claim 7, wherein the second half counter is one bit larger than the first half counter for determination readout of the sign information.

9. The digital harmonic rejecting phase detector of claim 8, wherein the sign information gate steers a clock pulse train to overflow the second half counter, or the number of clock pulses that elapse from second half counter overflow until next transfer from the first half counter is gate initiated.

10. The digital harmonic rejecting phase detector of claim 7, wherein counter control is sequentially: the first half counter is cleared by a first control signal with a detector clock signal from the clock control gating circuit means then being fed to the first half counter through the first half cycle of fr; a control transfer signal activates complement transfer gating circuit means for transfer of the 1''s complements of the first half counter content to the second half counter; the second half counter then actually counts from the number transferred by said complement gating means until the next said first control signal with the resulting number then gated to an output as a pulse train during the next successive first half cycle of the reference signal fr.

说明书全文

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Digital harmonic rejecting phase detector

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