BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the automatic compensation of phase variations in the delay element of a differentially coherent signal detector used for demodulation of phase shift keyed signals of arbitrary even order.

2. Description of the Prior Art

Binary phase shift keying (PSK) modulation is widely used in data communications. This modulation technique references the phase associated with a particular bit to the phase associated with a prior bit. As an example, if the phase of the Nth bit is X then the phase of the next bit will be X+90° if this next bit is a 1 and X-90° if this next bit is a 0, or vice versa. Or, if X is the phase of the Nth bit then the phase of the next bit will be X if this next bit is a 1, and X+180° if this next bit is a 0, or vice versa.

There are two basic approaches towards demodulating these signals. One method involves coherent signal detection using a local reference carrier as shown in FIG. 1. The received signal at 10, sin (WT+PH), is mixed by mixer 11 with a signal cos (WT) from a local reference oscillator 12, where W is the frequency, T is the time and PH is the phase angle. The output of mixer 11 at 13 is 1/2 sin (PH)+1/2 sin (2WT+PH). The phase of the received signal can be extracted from the baseband portion of this signal, 1/2 sin (PH). This technique involves comparing the phase of the received signal with the phase of a local reference carrier.

The main difficulties with this approach involve synchronizing the phase and matching the frequency of the local carrier with that of the original transmitter carrier.

A second approach for demodulating these signals involves a differentially coherent signal detection scheme as shown in FIG. 2. The received signal at 20, sin (WT+PI), where PI represents the phase angle, is split by hybrid splitter 21. The inphase portion is applied to delay element 22. The output of the delay element, the delayed signal sin (WT+PJ), where PJ represents the phase of the delayed signal, is connected to the input of mixer 23. The quadrature portion of the signal from hybrid splitter 21, cos (WT+PI), is fed to mixer 23. The output of mixer 23 is 1/2 sin (2WT+PI+PJ)1/2 sin (PI-PJ). The relative phase shift between the received bit and the prior bit can be extracted from the baseband portion of the signal, 1/2 sin (PI-PJ), emerging at 24 from mixer 23. This technique involves comparing the phase of the received bit with the phase of a prior bit. No local reference oscillator is needed; however, the phase of the prior bit must be saved for comparison. This can be accomplished by a delay element.

For optimal detection, the signals associated with the current and prior bit must simultaneously arrive at mixer 23. To accomplish this, the time delay introduced by the delay element 22 must be stable. Unfortunately, this stability is affected by temperature, age, and fluctuations in the frequency of the signal. The purpose of this invention is to insure maximum signal at the phase detector by automatically compensating for phase shifts introduced by the delay element.

A prior art search was conducted and the following patents were uncovered: U.S. Pat. Nos. 4,055,814; 3,919,653; 3,911,219; 3,906,376; 4,100,499; 3,787,775; 3,993,956; and 3,550,021 all require a voltage controlled oscillator. My invention uses differential coherent detection and does not require such a local reference oscillator.

U.S. Pat. Nos. 3,990,015; 3,991,377; 2,944,939; 3,838,350; and 3,794,921 all use delays for demodulation, but none of these systems provide a means to compensate for phase shift variations in the delay as does my invention.

U.S. Pat. Nos. 4,088,957; 3,818,346; and 3,843,931 do not use delays for demodulation nor do they have a phase shift correction mechanism as does my invention.

U.S. Pat. Nos. 3,305,798 and 4,053,932 do not involve coherent signal detection and are thus not applicable.

U.S. Pat. No. 4,091,331 utilizes a phase error predictor which requires the recovery of the clock signal. My invention operates directly with the signals and requires neither clock recovery nor bit synchronization.

U.S. Pat. No. 4,041,533 compensates for a variable delay in an analog video baseband signal; it can not be used to detect phase shift keyed signals or delay such signals. Unlike the present invention, the circuit requires introduction of reference pulses.

SUMMARY OF THE INVENTION

A binary phase shift keyed (PSK) signal (A) is split. One portion (B) is delayed by n bit periods. The other portion (C) is fed to a variable phase shifter. The delayed and the phase shifted portions are each split.

One portion of the delayed signal (B) is mixed with a portion of the phase shifted signal (C) by a mixer 55 which serves as a phase detector. The result is low pass filtered to form a signal dependent on the relative phase difference between the delayed signal (B) and the phase shifted portion (C), thus recovering the phase shift keyed information.

The other portion of the delayed signal (B) and the phase shifted signal (C) are fed to a phase tracking circuit. The delayed signal (B) is split and fed to two mixers 62 and 61. The phase shifted signal (C) is fed to a 90° hybrid to produce an inphase and a quadrature signal. The inphase portion is fed to mixer 62 while the quadrature signal is fed to mixer 61. The results from the mixers 62 and 61 are low passed and fed to a multiplier to produce a signal dependent on the phase difference between the delayed (B) and phase shifted (C) signals but independent of the keying induced phase shift. The signal is conditioned and used to control the variable phase shifter as part of a negative feedback loop which compensates for any phase shifts introduced by the delay element because of age, temperature, frequency shifts or other factors. This maximizes the signal from the phase detector.

In the case of quadraphase shift keyed signals, the phase detector, mixer 55, is replaced with a quadrature detector, and inputs of the phase tracking circuit are first fed to frequency doublers. The frequency doublers effectively reduce the quadraphase shift keyed signal to a binary phase shift keyed signal which the phase tracking circuit can operate on.

The phase shift keyed signals of this invention can have any a.c. frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other more detailed and specific objects and features of the present invention are more fully discussed in the following specification, reference being had to the accompanying drawings, in which:

FIG. 1 is a block diagram of a prior art coherent signal detection scheme for PSK which uses a local reference oscillator to extract the phase of the received signal;

FIG. 2 is a block diagram of a prior art differentially coherent signal detection scheme for PSK which extracts the relative phase between the current and a delayed signal;

FIG. 3 is a block diagram of a differentially coherent detector of the present invention with a variable phase shifter and phase tracking circuit to compensate for phase shifts introduced by the delay element; and

FIG. 4 is a block diagram of a differentially coherent signal detector of the present invention for quadraphase shift keyed signals.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 shows a phase tracking circuit for a differentially coherent signal detector which maximizes the detected signal by compensating for phase shift variations introduced by the delay element 52. Splitters 51 and 53, delay 52, variable phase shifter 56, 90° hybrid splitter 57, mixer 55, and low pass filter 59 form a differentially coherent signal detector. A binary phase shift keyed signal of the form sin (WT+PI) is introduced to the differentially coherent detector at 50. W represents the frequency, T the time, and PI the phase of the current bit. This signal is split by splitter 51.

One portion is fed to a delay element 52 which has a delay equivalent to n bit periods. The output of the delay element 52 can be represented as sin (WT+PJ+PD). PJ represents the phase associated with the previous bit and PD represents the phase error introduced by delay element 52. This signal is split by splitter 53. One portion is fed to phase tracking circuit 72 via connection 54. The other portion of the signal is fed to a mixer 55.

The other portion of the signal from splitter 51 is fed to a variable phase shifter 56. The output of phase shifter 56 is represented by sin (WT+PI+PS) where PS is the phase shift introduced by the variable phase shifter 56. This signal is split by a 90° hybrid 57. The inphase portion of the signal, sin (WT+PI+PS), is fed to phase tracking circuit 72 via connection 58. The quadrature portion of the signal, cos (WT+PI+PS), is fed to mixer 55 which functions as a phase detector. The output of mixer 55 is cos (WT+PI+PS).sin (WT+PJ+PD). This is equal to 1/2 sin (2WT+PI+PS+PJ+PD)-1/2 sin (PI-PJ+PS-PD).

This signal is fed to a low pass filter 59. The resulting signal is -1/2 sin (PJ-PJ+PS-PD). To maximize the coherent detection of this signal, the phase variation introduced by phase shifter 56, PS, should equal the phase error of delay 52, PD, or differ from it by 180°. This adjustment of the variable phase shifter 56 is the responsibility of phase tracking circuit 72 to be described. When the phase shifter 56 is adjusted correctly, the output of low pass filter 59 will be -1/2 sin (PI-PJ). Since the phase PI is either 90° or -90° relative to that of PJ, the output of filter 59 is either -1/2 or 1/2. These are interpreted as either "1" and "0", respectively, or "0" and "1", respectively, depending on the coding system employed.

Splitter 60, mixers 61 and 62, 90° hybrid shifter 63, conditioning amplifier 64, low pass filters 69 and 70, and multiplier 65 form phase tracking circuit 72. The delayed signal, sin (WT+PJ+PD), is fed from splitter 53 via connection 54 to splitter 60. One portion of this signal from splitter 60 is fed to mixer 61 while the other portion is fed to mixer 62. The inphase portion of the phase shifted signal, sin (WT+PI+PS), is fed from hybrid splitter 57 via connection 58 to hybrid splitter 63.

The inphase portion of the signal sin (WT+PI+PS) from hybrid splitter 63 is fed to mixer 62 while the quadrature portion, cos (WT+PI+PS), is fed to mixer 61. The output of mixer 61 is 1/2 sin (2WT+PJ+PD+PI+PS)-1/2 sin (PI+PJ+PS-PD). This is low passed by filter 69 to produce -1/2 sin (PI-PJ+PS-PD). This is fed to multiplier 65. The output of mixer 62 is 1/2 cos (PI-PJ+PS-PD)-1/2 cos (2WT+PJ+PI+PS+PD). This is low passed by filter 70 to produce -1/2 cos (PI-PJ+PS-PD). This is fed to multiplier 65. The output of multiplier 65 is 1/8 sin (2(PI-PJ)+2(PS-PD)).

For the embodiment where the difference between PJ and PI is either 90° or -90°, the 2(PI-PJ) term drops out, which leaves -1/8 sin 2(PS-PD), which is independent of the phase shift keyed modulation but dependent on the difference between the delay induced phase variation on connection 54 and the shifter induced phase variation on connection 58. This signal is fed to a conditioning amplifier 64 which scales the signal. The output of this amplifier is fed by connection 66 to variable phase shifter 56. This forms a phase tracking loop which maximizes the detected signal by providing a negative feedback which adjusts phase shifter 56 to compensate for any phase variations introduced by delay 52. The time constant of the loop is governed by the characteristics of amplifier 64.

Assuming that the variable phase shifter 56 produces a phase shift proportional to the signal on connection 66, the loop operates in the following manner.

If the variable shifter induced phase variation of the signal on connection 58, PS, is equal to the delay induced phase variation of the signal on connection 54, PD, then the output of multiplier 65 will by -1/8 sin (2×0) which is equal to 0. The output of amplifier 64 will also be 0 and the phase will not be changed by shifter 56.

If PS is larger than PD by E, where E is a slight angular deviation, then -1/8 sin (2E) will be fed from multiplier 65 to amplifier 64. Amplifier 64 scales this to produce a signal proportional to -sin (2E) which causes shifter 56 to decrease PS. This continues until PS is equal to PD.

If PS is slightly smaller than PD by E then +1/8 sin (2E) will be fed from multiplier 65 to amplifier 64. Amplifier 64 scales this to produce a signal proportional to +sin (2E) which causes shifter 56 to increase PS. This continues until PS is equal to PD.

The loop is also stable if the phase difference between PS and PD is ±180°. For the case where PS-PD=180°, the output of multiplier 65 is -1/8 sin (2×180°)=0. The output of amplifier 64 is 0 and the phase of shifter 56 is not changed. If PS is larger than PD by 180+E° then the output of multiplier 65 is -1/8 sin (360+2E) which is equal to -1/8 sin (2E). The output of amplifier 64 is proportional to -sin (2E). Shifter 56 then decreases PS. This continues until PS-PD equals 180°.

If PS is larger than PD by 180-E° then the output of multiplier 65 is -1/8 sin (360-2E) which is equal to +1/8 sin (2E). The output of amplifier 64 is proportional to sin (2E) which causes shifter 56 to increase PS. This continues until PS-PD equals 180°.

The loop is unstable if PS-PD is equal to 90°. The loop will force PS-PD=90+E° to PS-PD=180° while PS-PD=90-E° will be forced to PS-PD=0°. Similarly, PS-PD=270° is an unstable condition. The loop will force PS-PD=270+E° to PS-PD=360°=0 while PS-PD=270-E° will be forced to PS-PD=180°.

The phase tracking circuit 72 in conjunction with variable phase shifter 56 forms a servo loop which keeps the phase difference between the shifted and delayed portions of the signal in the coherent detector, PS-PD, equal to either 0° or 180°. This loop automatically compensates for any phase shifts, PD, introduced by delay 52 because of temperature, age, or other factors.

This maximizes the detected signal emerging at 71. This maximized signal will either be -1/2 sin (PI-PJ) or -1/2 sin (PI-PJ+180) (which equals 1/2 sin (PI-PJ)), depending on whether PS-PD=0° or 180°. This leads to a "1" or "0" ambiguity which can be easily resolved by the coding.

For the embodiment where the signaling format places the (N+1)st bit in phase or 180° out of phase with the Nth bit, the output of multiplier 65 is now 1/8 sin 2(PS-PD), which has the opposite sign from the previous case. Under these conditions the stable points for the loop occur when PS-PD=±π/2, ±3π/2 and the unstable points occur when PS-PD=0, ±π. Thus the phase correction loop automatically introduces a 90° phase shift between the delayed and undelayed signals; maximum output is still obtained from mixer 55.

This technique, which compensates for phase shifts introduced by the delay in a differentially coherent signal detector, can be extended for use with quadraphase shift keyed (QSK) modulation. Such an embodiment is shown in FIG. 4. In quadraphase modulation, the phase differential of the new bit pair is either X+0°, X+180°, X+90°, or X-90° relative to the phase differential X of the signal associated with the previous bit pair. The modulated signal is fed to splitter 81 at 80. One portion of the signal is fed to delay 82. The output of delay 82 is fed to splitter 83. One portion of the signal is fed to a frequency doubler 92. The output of doubler 92 is fed by a connection 54 to phase tracking circuit 72. The other portion of the signal from splitter 83 is fed to a hybrid splitter 84. The inphase portion, sin (WT+PJ+PD), of this splitter is fed to a mixer 85 while the quadrature portion, cos (WT+PJ+PD), is fed to a mixer 86.

The other portion of the signal from splitter 81 is fed to a variable phase shifter 91. The output of this shifter is fed to a hybrid splitter 90. The inphase portion is fed to a frequency doubler 93 which is in turn connected to phase tracking circuit 72 via connection 58. The quadrature portion from splitter 90 is fed to a splitter 89. Portions of the signal from splitter 89, cos (WT+PI+PS), are fed to mixers 85 and 86. The output of mixer 85 is 1/2 sin (2WT+PI+PS+PJ+PD)-1/2 sin (PI-PJ+PS-PD). This is low passed by filter 87 to produce -1/2 sin (PI-PJ+PS+PD) at 95. The output of mixer 86 is 1/2 cos (2WT+PI+PS+PJ+PD)-1/2 cos (PI-PJ+PS-PD). This is low passed by filter 88 to produce -1/2 cos (PI-PJ+PS-PD) at 96.

Hybrid splitter 84, splitter 89, mixers 85 and 86, and low pass filters 87 and 88 form a quadrature detector.

Suppose PS-PD equals 0°. Then if PI-PJ is equal to 0°, 180°, 90°, or -90°, respectively, the output at 95 will be 0, 0, -1/2, 1/2, respectively, while the output at 96 will be -1/2, 1/2, 0, 0, respectively. Thus, the outputs of 95 and 96 can be used in conjunction to distinguish the four phases used in quadrature shift keying.

The signals fed to phase tracking circuit 72 in FIG. 4 by connections 54 and 58 are twice the frequency of those shown in FIG. 3. The hardware of the phase tracking circuit 72 is not changed; however, the frequency doublers 92 and 93 affect the output of the tracking circuit on connection 66.

Because of the frequency doublers 92 and 93, the output of mixer 61 is 1/2 sin (4WT+2PJ+2PD+2PI+2PS) -1/2 sin (2PI-2PJ+2PS-2PD). The output of mixer 62 is 1/2 cos (2PI-2PJ+2PS-2PD)-1/2 cos (4WT+2PJ+2PD+2PI+2PS). The output of multiplier 65 is 1/8 sin (4(PI-PJ)+4(PS-PD)). PI-PJ is either 0°, 180°, -90° or 90°. Four times this is 0°, 720°, -360°, or 360°. These are all multiples of 360°, so the output of multiplier 65 simplifies to 1/8 sin (4(PS-PD)). This signal is independent of the quadraphase shift keyed modulation, but dependent on the difference between the delay induced phase variation and the shifter induced phase variation.

The loop formed by phase tracking circuit 72 and variable phase shifter 91 is stable when PS-PD is equal to 90°, -90°, 180°, or -180°. The loop is unstable if PS-PD is equal to 45°, -45°, 135°, or -135°. In the case of instability, the loop will settle at one of the stable values. This loop will thus keep the phase of the delayed and shifted portions of the signals in the differentially coherent detector at either 90°, -90°, 180°, or -180°. This introduces angular offsets into the output at 95 and 96, leading to "1" or "0" ambiguities which can be resolved by the coding.

The technique of the present invention can be extended to a phase shift keyed signal having an arbitrary even order by replacing the detector portion of the circuit (items 84 through 89 in the case of quadraphase shift keying) with a detector capable of detecting that particular order of phase shift keying, and by replacing frequency doublers 92 and 93 with frequency multipliers of the appropriate magnitude. For example, for hex phase shift keying, frequency triplers are used at 92 and 93; for octal phase shift keying, frequency quadruplers are used at 92 and 93; etc. In general, for Nth-order phase shift keying, items 92 and 93 must multiply the frequency by a factor of N/2.

The above description is included to illustrate the operation of the preferred embodiments and does not limit the scope of the invention. The scope of the invention is to be limited only by the following claims. From the above discussion many variations will be apparent to one skilled in the art that would yet be encompassed by the spirit and scope of the invention.