The present invention is concerned with the measurement of characteristics of a device under test (DUT).

Generally the impedance, gain, phase or quality of a DUT, for example a resistor, a capacitor, an amplifier, a digital-to-analog converter etc. can be measured by providing an a.c. signal to the DUT and then comparing the input and output a.c. signals of the DUT or analyzing the output a.c. signal of the DUT. For measurements at high frequency it may be required that the high frequency output signal of the DUT be converted to an intermediate frequency signal at lower frequency, using a selected local frequency signal. When it is required that the high frequency output signal of the DUT be sampled and measured at high accuracy, the local frequency signal should have high resolution in frequency and be pure. In the prior art, however, it was difficult to measure the characteristics of the DUT accurately because the required accuracy and resolution make the known measurement circuits, especially the circuitry for generating the desired local frequency signal, remarkably complicated.

The object of the present invention is to provide a circuit for measuring characteristics of a DUT with high accuracy while allowing for comparatively simple circuit construction.

In accordance with claim 1, this objective is met by providing an apparatus for measuring characteristics of the DUT comprising first generating means for generating the input signal as a periodic signal having a period T, second generating means for generating a sampling signal as a periodic signaT having a period t = nT + T/m, where n and m are integers, first sampling means for receiving the output signal from the DUT and the sampling signal, second sampling means for receiving the input signal to the DUT and the sampling signal, first converting means for converting the output signal of the first sampling means to first digital values, second converting means for converting the output signal of the second sampling means to second digital values, and calculating means coupled to the first and to the second converting means for calculating characteristics of the DUT from the first and the second digital values.

Both signal sources may be coupled to one single crystal oscillator for both, and in accordance with claim 2 one or both may be con= structed as a fractional N oscillator such as is known from US Patent 3,928,813.

The embodiment in accordance with claim 3 further improves measurement accuracy by reducing errors arising from jitter, phase noise etc. In the embodiment of claim 3, the a.c. signal of a crystal oscillator (the first signal source) is applied directly to the DUT, and the second signal source is coupled to the crystal oscillator and includes a phase locked loop which provides for higher accuracy of the sampling signal.

In all embodiments the signals are sampled and converted to digital values by A/D converters and input to a microprocessor. The input signals and the output signals of the DUT are analyzed by the microprocessor to calculate the characteristics of the DUT.

The invention will now be described in detail with reference to the accompanying drawings.

• Figure 1 is a block diagram of a circuit for measuring phase and amplitude of a.c. signals passed through a DUT.
• Figure 2 shows another circuit for the same purpose including a phase locked loop.
• Figure 3 explains the sampling operation for sampling a.c. signals in any one of the circuits shown in Figures 1 and 2.

Figure 1 shows a circuit for measuring RF signals applied to and transmitted by a device under test (DUT). The circuit operates to perform a measurement as follows. Units 10 and 20 are first and second signal sources of the circuit, and both signal sources may include fractional N oscillators which are coupled to an output signal of a crystal oscillator 30 and which can provide highly accurate a.c. signals for use in the circuit. Element 12 is a DUT, elements 13 and 15 are sampler circuits for sampling input and output a.c. signals at the DUT. In the present circuit, sampler 13 under control by the output signal of the second signal source 20 samples and holds the momentary amplitude of the output signal passed through the DUT. Sampler 15 under control by the output signal of the second signal source 20 samples and holds the momentary amplitude of the output signal of the first signal source 10, which is applied to DUT 13. The desired information, for example impedance, resistance, capacitance etc. can be obtained by calculations from the momentary amplitude values of these two signals with a microprocessor 17, to which end the momentary amplitude values are respectively converted to digital values with A/D converter 14 and 16.

It may, however, in certain applications such as a measurement of the input to output transfer characteristics of circuits such as an amplifier or a digital-to-analog converter not be necessary to utilize the output signals of A/D converter 16 as will be apparent to persons that are knowledgeable in the art.

The sampling signal generated by signal source 20 serves to define sampling points in time in accordance with the following equation (1) wherein the output period of the first signal is T seconds and the period of the sampling signal is t seconds.

In equation (1) m and n are positive integers and m is the number of samplings during the period T. Accordingly, the amplitude values Ap for the pth harmonic of the first signal can be calculated by application of a Digital Fourier Transformation (DFT), if a number m of data points of the first signal are measured during period T. The discrete Fourier Transform may be expressed as follows:

Furthermore the amplitude values of higher order harmonics may be calculated by expanding the Fourier series. By such an amplitude measurement the characteristics of an amplifier or a DAC can be measured. It is also readily seen that if a two channel sampler is used, the phase, gain or impedance information available between these channels can be analyzed.

If, for example, the frequency of the first signal is 100 MHz, its period T is 10 ns. By substitution into equation (1), setting n to the value of 100 and setting m to the value of 128, the period of the sampling signal t may be calculated as follows:

This means that one sampling is done for each 100 periods of the signal to be sampled, with each sampling point being relatively offset from the preceding sampling point (in relation to the signal to be sampled) by 1/128 of the period of the signal to be sampled, i.e. by T/128. In other words, one sampling occurs within each 100th period of the signal to be sampled, and the sampling points are offset from the start of the period of that signal in increments of T/128. The resulting frequency of the sampling signal is 999.92188... kHz. Therefore it is required that the sapling signal be generated by an oscillator having high resolution and accuracy.

It is known that fractional N oscillators can settle on any rational frequency value with a resolution of 1/10¹⁶ and thus generate highly accurate sampling signals easily.

Figure 2 shows a modification of the circuit shown in Figure I. Elements shown in Figure 2 have the same designation as in Figure 1 if their function is equivalent. If, as in Figure 1, the output signal of a first fractional N oscillator is applied directly to the DUT and the output of a second fractional 14 oscillator is used as a sampling signal, slight measurement errors may occur from jitter and phase noise caused by the fractional N oscillators. In Figure 2 the a.c. signal of a crystal oscillator 30 is applied to the DUT 12 via a filter 11. Output and input signals of the DUT 12 are respectively applied to an input terminal of a sampler 13 and a sampler 15. The second input terminals of samplers 13 and 15 receive sampling signals defined in accordance with equation (1) above which are generated as follows.

The output signal of crystal oscillator 30 is applied to a fractional N oscillator 25, and also applied to one input terminal of a phase detector 21. The phase detector is included in a phase locked loop (PLL) further including a filter 22 and a voltage-controlled crystal oscillator 23 as shown in Figure 2. The purpose of the phase locked loop is to set the frequency of the sampling signal to the value of the fractional N oscillator 25. Thus a highly accurate sampling signal may be generated at any desired frequency 1/t without relatively large noise to cause measurement error, and may be applied to the samplers 13 and 15, by locking its frequency to the frequency of fractional N oscillator 25.

The a.c. signal applied to DUT 12 is generated directly by crystal oscillator 30 which further improves the accuracy of measurement. The output signal of crystal oscillator 30 may be applied to DUT 12 via a frequency divider.

Figure 3 is a timing chart which explains the sampling operation taking place in the measurement circuit shown in Figures 1 and 2. Curve A is representative of an input signal to DUT 12, and curve B represents sampling signals. The momentary amplitude of the a.c. signal having a period of T is obtained at each of the successive sampling points falling on times t = nT + T/m as shown in Figure 3. Thus, by dividing the period T into m offset increments T/m sampling is performed at m different points within the period of the signal A. The data is converted by A/D converters 14, 16 and subsequently phase and amplitude of the input and output a.c. signals may be calculated by microprocessor 17 in accordance with the DFT algorithm.

For instance, the output frequency of crystal oscillator 30 may be 100 MHz (T = 10 ns) and the sampling frequency may be some value around 1 MHz. In particular the sampling frequency to be selected by the fractional N oscillator 25 is defined to divide the period of the 100 MHz frequency into m offset increments T/m for determination of the sampling times. If m is 100 and n is 10, the sampling frequency generated by fractional N oscillator 25 and voltage-controlled crystal oscillator 23 is 1/1.001 MHz which may be generated as a frequency of 999.0009990009990 kHz with a resolution of 1/10¹⁶. In this case the pull-in range of oscillator 23, or frequency deviation from the central frequency of oscillator 23 of 1 MHz, is about 1 kHz. Further, if n is the same and m is set to 1000, the sampling frequency would be 999.9900000999990 kHz. In this case the pull-in range of oscillator 23, or in other words the frequency deviation from the certral frequency of oscillator 23 of 1 MHz, is narrowed to 0.01 kHz. Accordingly, if a larger number of samplings m is selected, the number of samples taken to represent one signal cycle increases and the pull-in range, or deviation from center frequency, of voltage-controlled crystal oscillator 23 becomes narrower. The narrower the pull-in range becomes, however, the better the quality of the output signal of oscillator 23 will be because the jitter will be reduced. Therefore the measurement of a.c. signals with higher accuracy can obviously be expected.