Serial-parallel binary multiplication using pairwise addition专利检索-时钟树信号处理专利检索查询-专利查询网

Serial-parallel binary multiplication using pairwise addition

阅读：267发布：2022-01-04

专利汇可以提供Serial-parallel binary multiplication using pairwise addition专利检索，专利查询，专利分析的服务。并且A serial-parallel two''s complement binary multiplier circuit featuring a tightly clocked arrangement facilitating the formation of a product signal in an interval of duration shorter than the arrival interval for a serial multiplicand word. Hence, the multiplier circuit is capable of processing butted-word inputs in real time with only minor constraints on word formats. The multiplication algorithm features a pairwise summation of partial products on a least-significant-bit-first basis which gives rise to a tree-like structure of substantially identical circuit modules. Negative multiplicands are treated using a postmultiplication correction circuit.，下面是Serial-parallel binary multiplication using pairwise addition专利的具体信息内容。

权利要求

1. Apparatus for forming signals representing the final product of a first set of digit signals occurring in time sequence during respective time intervals representing a multiplicand and a second set of digit signals present during each of said input intervals representing a multiplier comprising 1. first means for forming digit product signals corresponding to the product of each digit of said multiplicand and each digit of said multiplier, 2. second means for forming for each digit of said desired final product sum signals representing the sum of pairs of said digit product signals which contribute to said digit value of the desired final product signal, and 3. third means comprising means for iteratively forming cumulative sums of pairs of sum signals contributing to said digit value of the desired final product signal, said iterations being performed at a rate equal to one for each input time interval, said pairs of sum signals operated on by said third means at the first iteration being those formed by said second means, said pairs of sum signals operated on at subsequent iterations being those formed by said third means during the immediately preceding iteration.

2. second means for forming for each digit of said desired final product sum signals representing the sum of pairs of said digit product signals which contribute to said digit value of the desired final product signal, and

2. means for applying consecutive digit signals of said M-digit multiplicand signal to the input of the first of said delay units during respective consecutive input time intervals,

2. Apparatus according to claim 1 wherein said third means further comprises means for increasing at each iteration said sum of pairs of sum signals by amounts representative of carry signals associated with one or more digits of lower significance in said desired final product.

3. third means comprising means for iteratively forming cumulative sums of pairs of sum signals contributing to said digit value of the desired final product signal, said iterations being performed at a rate equal to one for each input time interval, said pairs of sum signals operated on by said third means at the first iteration being those formed by said second means, said pairs of sum signals operated on at subsequent iterations being those formed by said third means during the immediately preceding iteration.

3. N ordered AND circuits, each having a first and second input and an output,

3. Apparatus according to claim 1 wherein said third means comprises an array of substantially identical modules interconnected in a tree structure.

4. Apparatus according to claim 3 wherein each of said substantially identical modules comprises an adder for forming the sum of two-digit signals and carry signals.

4. means connecting the first input of the first N-1 of said AND circuits to the input of the corresponding one of said delay units, and means for connecting the first input of the Nth of said AND circuits to the output of the (N-1)th of said delay units,

5. means for simultaneously applying the ith digit signal of said N digit multiplier signal to the second input of the ith of said AND cricuits, i 1,2, . . . ,N,

5. Apparatus according to claim 4 wherein said tree structure comprises N hierarchical levels where N log2 M-1, and M is the number of digits in said multiplier signal.

6. Apparatus according to claim 5 further comprising, in each identical module delay meanS associated with each adder for providing during each multiplicand input signal interval the result of the sum formed in said associated adder during the immediately preceding input interval.

6. an array of substantially identical modules each having two inputs and one output lead interconnected in a decreasing tree structure of ordered stages for iteratively summing in pairwise fashion the signals generated at the outputs of said N AND circuits, said array comprising N/2 modules at the first stage and one module at the last stage, the sequence of signals appearing on the output lead of said one module at said last stage being said product signal sequence.

7. Apparatus for generating a sequence of signals representing the product of an M-digit multiplicand and an N-digit multiplier, where said multiplicand and multiplier are represented respectively by M-digit and N-digit signals, comprising

8. Apparatus according to claim 7 wherein each of said modules comprises a three-input adder circuit for generating sum and carry signals, means for storing a carry signal generated by said adder during the immediately preceding input time interval, and means for applying said stored carry signal to one of said three inputs during a current input time interval.

9. Apparatus according to claim 8 wherein each of said modules further comprises means for applying said sum signals generated by said adder after a delay of one input time interval to one of said adders at the subsequent stage, said sum signals generated by said adder at said last stage being said signals representing said product.

10. Apparatus according to claim 8 further comprising correction means for forming a sequence of correction signals corresponding to the successive cumulative sums of the digits of said multiplier word, and means for selectively combining said correction signals with the output signals appearing on the output lead of said module at said last stage of said tree structure whenever said multiplicand has a negative sign thereby to generate a corrected product signal.

11. Apparatus for generating a corrected product signal resulting from the 2''s complement multiplication of a multiplier and a multiplicand when said multiplicand has a negative sign comprising A. means for forming a sequence of signals corresponding to successive cuculative sums of the digit values of said multiplier, and B. means for bit-wise adding each of said cumulative sum signals to a corresponding bit signal of said uncorrected product.

12. Apparatus according to claim 11 wherein said means for forming comprises a three-input adder for generating sum and carry signals, means for sequentially applying to one input of said adder during consecutive time intervals signals representing consecutive multiplier digits, means for storing carry signals generated by said adder during the immediately preceding time interval and for applying said carry signals to a second input of said adder during the current interval, and means for applying to the third input of said adder during the current time interval a replica Of the sum signal generated by said adder during the immediately preceding time interval.

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Serial-parallel binary multiplication using pairwise addition

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