BACKGROUND OF THE INVENTION

Since the introduction of the first microprocessor in the early 1970's, the increased demand for faster and smaller digital processing elements has spurred the rapid growth of digital technology. Large thrusts were made to make this industry both innovative and economical. Today, there are hosts of devices that operate in the digital domain: static and dynamic memories, EPROM's, PAL's, microprocessors and controllers as well as gate-arrays and ASIC's (Application Specific Integrated Circuits). The cost and turn-around time for producing some of these chips is very small.

There still remains a desire to produce faster and smaller digital chips, but the technology has yet to be discovered that will extend the range of these devices beyond their current capability. Since the availability of memory and microprocessors is abundant, efforts are being made to update interface technology. Data must be in digital form, hence the need for fast and efficient analog-to-digital converters as well as digital-to-analog converters. These comprise the information interface to the real world. In addition to the digital processing and data conversion elements, there is a need for more efficient and innovative sensors. Just as the digital industry sought more creative, cheaper designs, the analog and sensor designers did also.

The efforts of the digital industry made possible the complicated processing of silicon into an economically attractive technology. This industry has dictated the direction of both analog circuit and sensor designers. If a design can be implemented using conventional digital IC technology or by a slight modification, then it is advantageous to do so. This trend can be observed in the frequent use of CMOS technology in analog circuit design, though its origins were in digital design. In this decade, sensor designers have taken advantage of some of the unique processing aspects of silicon. The ability to precisely etch silicon into diaphragms and other structures makes possible total integration of sensor, interface, and information processing on one chip. The economic advantages of system integration are enormous.

A common type of sensor is the variable capacitance device. Capacitance of a capacitor is equal to εA/d where ε is the dielectric constant, A is the area of the plates, and d is the gap thickness. Any change or combination of changes in the three variables can cause a capacitance change that can be detected. As an example, a pressure transducer can be formed by a diaphragm which supports one plate of the capacitor. Movement of the diaphragm changes the gap of the capacitor and thus its capacitance. As another example, shear force can be detected by lateral movement of one plate relative to another. That movement can vary the effective area of the capacitor. Further, the dielectric constant can be modified by chemical or thermal conditions or the like. Other capacitive sensors can detect tactile pressure or acceleration.

Unfortunately, sophisticated read-out circuitry must be employed to detect small capacitance changes in small capacitors due to the presence of large parasitic capacitances. The challenge is to design circuitry that is compatible with regular MOS fabrication and silicon micromachining processes and which can overcome the problems of parasitics and noise. Present systems employ both ac and dc techniques to sense capacitance change. However, the sense capacitors employed are much greater than the stray parasitics. As silicon diaphragms are scaled, new circuitry must be developed to handle smaller sense capacitors. This is due to the ability of semiconductor processes to scale horizontally across a wafer. If a structure can be built and be operational on a smaller scale, then it is more economical to do so since the cost of processing depends on area.

DISCLOSURE OF THE INVENTION

The present invention relates to a system for sensing a parameter which causes a change in capacitance of a sensing capacitor. The system described incorporates an analog-to-digital converter in the capacitance sensor to provide a direct digital output. The system may avoid errors which might result from parasitic capacitances, amplifier voltage offset, injected charge and charge hysteresis.

The system uses a charge redistribution technique to sense capacitance. A definite amount of charge is isolated on a node which is electrically coupled to the sensing capacitor. The distribution of that charge on the node is then modified by at least one voltage applied to the sensing capacitor. Voltage change with the redistribution of charge is sensed by a comparator which is part of a successive approximation analog to digital converter loop. By means of that loop, a feedback signal is applied to the comparator.

In a preferred system, both a reference capacitor and sensing capacitor are coupled to the node. An analog output from the successive approximation loop is also coupled to the node through a coupling capacitor. The node is connected to the inverting input of the comparator. A charge is sampled by applying a first set of voltages to the reference and sensing capacitors as a switch connected in parallel with the comparator is closed. The resultant charge on the capacitors is isolated as the switch is opened. The voltages applied to the reference and sense capacitors are changed to modify the distribution of the isolated charge and any difference between the capacitances of the two capacitors results in a change in voltage on the node. That change in voltage is then nulled by the successive approximation loop.

Many measurement sequences in which voltages are applied to the capacitors are possible. In many cases, it is preferable to establish the charge on the node with the voltage briefly applied to the sensing capacitor. Thereafter, the voltage applied to the sensing capacitor during the successive approximation routine may be best set at zero to minimize changes in the voltage during the routine. In some systems, both the reference and sensing capacitor may respond to the sensed parameter for a differential output. It may be desirable to apply voltages other than zero to the capacitors to establish the isolated charge and thereafter apply zero volts to both capacitors during the successive aproximation routine.

A significant aspect of the system is the ability to calibrate the circuit to avoid errors due, for example, to charge injected by the isolating switch. To that end, the charge may be established on the node and the switch may then be opened without changing the voltages applied to the capacitors on the node. The voltage which then occurs on the node, which may result from charge injected by opening the switch, can then be measured by the successive approximation loop in nulling the voltage. A calibration signal can then be stored digitally and subsequently be applied to the coupling capacitor as charge is established on the node in subsequent measurements. That charge established on the node directly offsets the charge subsequently injected by the switch. Mismatch between the sensing and reference capacitors can be corrected in a similar manner.

Other errors may result from hysteresis of the reference and sense capacitors. That hysteresis can be measured by modifying the distribution of charge in dual sequences. The difference between changes in voltage on the node during the two sequences can be indicative of capacitance hysteresis.

Although the invention may be applied to many forms of capacitance sensors, a novel sensor structure has been developed for pressure sensing. In that sensor, the sensing capacitor is formed of a diaphragm having a conductive plate which spans a gap of a first area. A reference capacitor is formed of a plurality of diaphragms spanning respective gaps. Each gap of the reference capacitor diaphragm is of an area substantially less than of the area of the sensing capacitor diaphragm. Each diaphragm has a conductive plate and the plural plates are electrically coupled to electrically match the sensing capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

FIG. 1 is a circuit diagram for measuring the change in capacitance of a capacitive sensor embodying the present invention.

FIG. 2 is view of the circuit of FIG. 1 with the switches repositioned.

FIG. 3 illustrate a sensor in lateral movement of a plate results in differential capacitance charges.

FIG. 4 is a cross sectional view showing the construction of a reference capacitor and a sensor capacitor respectively on a chip embodying the present invention.

FIG. 5 is an illustration of an alternative switch arrangement for applying reference voltages to the capacitors of FIGS. 1 and 2.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to an electronic circuit which measures the change in capacitance of a sensing capacitor. The overall circuit produces an output in both digital and analog forms which is proportional to the capacitance change. Further, the output is free from errors caused by the effects of parasitic capacitance and may be made free of errors such as those resulting from charge injection from MOS switches.

A preferred method for measuring the change in capacitance of a capacitive pressure sensor can be explained by making reference to the circuit shown in FIG. 1. The method essentially comprises two steps. For the first step, a first switch S₁ is positioned to connect ground GND to an electrode 10 attached to the bottom plate 12 of a reference capacitor C_R. An electrode 14 connected to the top plate 16 of the reference capacitor C_R is connected through line 30 to the amplifier output by a coupling switch S_C. A sensor capacitor C_S having an electrode 18 attached to its top plate 20 is also connected to the amplifier output by the coupling switch S_C. The bottom plate 22 of the sensor capacitor C_S is similarly connected to a reference volta V_REF by a second switch S₂. A top plate 46 of a coupling capacitor C_C is also coupled to the node 24. The bottom plate 48 of the coupling capacitor C_C is connected to a variable voltage source on line 36, V_VAR =V.sub. DAC, initially set at zero volts. As a result of these connections, a charge Q₁ will be stored on the sensing capacitor C_S. Note that the voltage V_X at node 24 will equal zero volts because it is pulled to ground by the amplifier A through the switch S_C. Using a common node 24 for the electrodes 14 and 18, as shown in FIG. 1, the charge Q₁ stored on the capacitors C_S and C_R can be calculated as:

Q1 =-VREF CS                                (1)

The second step of the measurement comprises the step of switching the three switches S₁,S₂,S_C from their above positions. In other words, the first switch S₁ connects the bottom plate 12 of the reference capacitor C_R to the reference voltage V_REF, the second switch S₂ connects the bottom plate 22 of the sensor capacitor C_S to ground GND, and the coupling switch S_C opens. Opening switch S_C isolates the charge established on node 24 by the first setting of switches S₁ and S₂ Switching switches S₁ and S₂ results in a redistribution of the charge which has been isolated on the node 24. If the capacitance of the sensor capacitor C_S is equal to the capacitance of the reference capacitor C_R, then voltage V_x at the common node 24 will be equal to zero volts; otherwise, a non-zero voltage will be detected at the reference ground V_X.

The object of the second step is to apply a sufficient amount of voltage by the variable voltage source V_VAR to the coupling capacitor to force the voltage V_X to the initial value of zero volts. As a consequence of this step, the charge will be stored only on the reference capacitor C_R and the coupling capacitor C_C because both sides of the sensing capacitor C_S are at zero volts. Thus, the total charge Q₂ stored on the capacitors is:

Q2 =-VREF CR -VVAR CC             (2)

Assuming that the capacitors are ideal requires that

Q1 =Q2                                           (3)

because there would be a conservation of charge. Thus

-VREF CS =-VREF CR -VVAR CC  (4)

By setting Q₁ equal to Q₂ and solving for V_VAR in equation (4) the amount of voltage applied by V_VAR will be proportional to the capacitive difference of C_S and C_R. Thus,

VVAR =[VREF (CS -CR)]/CC          (5)

In practice, parasitic capacitance shown as C_p is inherent in any circuit. Parasitic capacitance can be created whenever two conducting layers overlap. However, the effects of the parasitic capacitance are cancelled in the above equations because it would add the same charge term to both Q₁ and Q₂.

The signal V_VAR is obtained during the second step by amplifier A (which may be a unity gain amplifier) and feedback circuitry including a successive approximation register 38 and a digital-to-analog converter 40. When the third switch S_C is in an open position, the amplifier A operates as a voltage comparator. In other words, voltage at the inverting input terminal 34 is compared with the voltage at a non-inverting terminal 44 which, in this case, is tied to ground. If the voltage V_X varies from zero volts, then the output 32 of the amplifier A saturates to a positive or negative saturation level depending on whether the voltage V_X is negative or positive respectively.

Whether the voltage V_X varies from zero volts depends on the capacitive values of the reference capacitor C_R and the sensor capacitor C_S. If the capacitances are equal, then there should be no voltage difference detected by the amplifier A. If the capacitive values of the capacitors are different, then the voltage V_X varies from zero volts. When the voltage V_X varies from zero volts, the amplifier A detects the difference and outputs a positive or negative saturation voltage. The output voltage produced by the amplifier A is applied to the SAR 38 which applies a digital signal to the DAC 40 to generate a voltage which will null the voltage V_X.

The SAR generates an initial digital value which typically is half its full range of values. That digital value is converted by DAC 40 to an analog signal which is applied to the node 24 through capacitor C_C. Because an exact match of the analog signal to the voltage due to the capacitive difference is unlikely, V_X will then be some value other than zero. Whether that value is above or below zero is sensed by the comparator to indicate whether the initial value from the SAR was too high or too low to provide an accurate offset. Based on the output from the comparator, the SAR makes another approximation which is applied to the node 24. That second approximation would typically be 1/4 or 3/4 the full range value depending on whether the last approximation was too high or too low. In this manner, successive approximations are made to obtain the output from the SAR and DAC which most closely offsets the voltage due to the capacitive difference. The comparator A, SAR 38 and DAC 40 thus operate as an analog-to-digital convertor which senses the change in voltage V_X due to charge redistribution in the second step.

Note that the coupling capacitor C_C provides for charge coupling between the output of the DAC and the input of the amplifier A. From equation 5 it can be seen that the capacitance C_C acts as a voltage divider which can increase the resolution of the system in response to small differences (C_S -C_R)

The final digital value of the signal applied to the DAC 40 represents a voltage that will be proportional to the capacitive difference between the sensor capacitor C_S and the reference capacitor C_R. In other words, if the SAR, DAC, and the operational amplifier are ideal, then the output voltage V_VAR from the DAC will precisely force the voltage V_X to zero volts. As a result, the output voltage V_VAR of the DAC 40 will be the voltage required to compensate for the proportional difference in capacitances of the sensor and reference capacitors. For example, if the sensor capacitor C_S were not equal to the reference capacitor C_R and the voltage of the reference ground V_X were less than zero volts, then a positive voltage would be required at the output of the DAC 40 to force the voltage of the reference ground V_X to zero volts.

Once the voltage of the reference ground V_X has been forced to zero volts, the charge observed at the common node 24 is as follows:

Q2 =-VREF CR -VDAC CC             (6)

By charge conservation,

Q1 =Q2                                           (7)

so that

-VREF CS =-VREF CR -VDAC CC  (8)

Solving for V_DAC

VDAC =[VREF (CS -CR)]/CC          (9)

Thus, the output voltage V_DAC of the DAC produces a voltage proportional to the capacitive difference of C_S and C_R.

It should be noted that the reference voltage V_REF and the ground GND could be set to any arbitrary, constant voltage values. However, it is preferred that the sensing capacitor be grounded during the second step. This is because the successive approximation routine requires an amount of time during which the sensed parameter may be varying. If the sensing capacitor were not grounded, the varying voltage V_X would complicate the successive approximation routine. However, with the sensing capacitor grounded, its changing capacitance does not affect V_X or the measurement at that time. The capacitance of the reference capacitor, on the other hand, is relatively stable. The charge on node 24 can be established and isolated during a very short increment of time in which switches S₁, S₂ and S_C are thrown to their first step positions to quickly establish a charge which is the basis of measurement. Thereafter, the switches are thrown to their second step positions. During the longer successive approximation routine, the reference potential is applied to the more stable reference capacitor and zero potential is applied across the sensing capacitor.

The above calculations are based on the assumption that the circuit is an ideal circuit. In reality, however, the ideal circuit cannot exist. In practice, offset voltage and finite resolution of the amplifier as well as DAC error and charge injected by the switches exist.

In the present circuit, the offset voltage of the amplifier A can be ignored. If the amplifier's offset voltage is not equal to zero volts, then the voltage V_X equals the amplifier's offset voltage. Since the above steps are done relative to the same voltage V_X, the offset voltage of the amplifier has no effect in the final output.

A potential source of error in the measurement is an amount of charge injected by the third switch S_C when it is opened. That injected charge can be measured by comparing the charge stored by the capacitor C_S before and after the third switch S_C is opened. When the switch is opened, an initial charge Q_OA is established on the node 24. The initial charge includes that stored on the reference capacitor C_R during the first measurement step noted above and the charge Q_SC injected from opening S_C. Thus, the initial charge Q_OA is:

QOA =-VREF CR +QSC                     (10)

Due to Q_SC, the voltage V_X will be other than zero after the switch S_C is opened. Without switching S₁ or S₂, the SAR circuit then establishes a voltage V_VAR,CAL which drives the voltage V_X back to zero. The charge on node 24 is then:

QOB =-VREF CR -VVAR,CALC C    (11)

As before, there will be a conservation of charge between the above steps; therefore,

QOA =QOB                                         (12)

Solving for the output voltage, V_VAR,CAL of the DAC which nulls the change in the voltage V_X due to Q_SC yields:

VVAR,CAL =-QSC /CC                          (13)

The digital value of this output voltage would appear at the output of the SAR at the end of the calibration measurement. This voltage is proportional to the injected charge Q_SC.

Preferably, the calibration value of the output voltage V_VAR,CAL is stored in the memory register 42. Its negative, instead of a zero output voltage V_VAR, is applied through C_C during the first step of subsequent capacitive measurements. -V_VAR,CAL applied to C_C during the first measurement step establishes a charge on node 24, when it is driven to zero volts through switch S_C, which is subsequently offset by the equal charge injected when switch S_C is opened. Subsequently, when V_X is driven to zero in the second measurement step by V_VAR,MEAS :

VVAR,MEAS =[VREF (CS -CR)]/CC     (14)

Because the injected charge can vary under varying test conditions, the voltage V_VAR,CAL used to calibrate the system for charge injection can be measured periodically.

Another error which can be corrected by the circuit is that of capacitance hysteresis. Due to hysteresis, the charge on the sense capacitor, for example, might not return to zero when the voltage across the capacitor goes to zero. This charge affects the voltage measured at V_X. The error voltage due to hysteresis can be determined by running dual sequences. In a first measurement sequence, for example, a voltage applied to C_R would be switched from zero to V_REF as the voltage applied to C_S is switched from V_REF to zero. In a subsequent test sequence, the voltages applied to the capacitors during the two steps of the measurement would be reversed. The measured voltages in the two test sequences would then be:

VVAR,MEAS,1 =[VREF (CS -CR)]/CC -[QSP CC ]                                                         (15)

VAR,MEAS,2=[VREF (Cr -CS)]/CC -[QRP /CC ](16)

where Q_SP and Q_RP are residual charges due to hysteresis polarization. The sum of those two measured values is then:

VP =(-QSP -QRP)/CC                     (17)

Thus, the system would allow for compensation for the hysteresis error. However, in most applications the charge due to hysteresis is insignificant, and correction for charge injection due to opening of the switch S_C is the only required error correction.

In the preferred embodiment, capacitive differences in small capacitances of integrated sensors are measured. With the above measuring technique, both digital and analog representations of the output voltage V_VAR, proportional to the capacitive difference between the reference capacitor C_R and the sensor capacitor C_S are available. The digital output voltage appears at the output of the SAR 38 while the analog ouput voltage appears at the output of the DAC 40.

The disclosed system utilizes an analog-to-digital converter in the form of comparator A, SAR 38, and DAC 40 as the voltage sensor for sensing the voltage on node 24. The analog-to-digital converter is thus an integral part of the detector circuitry. This has distinct advantages over a system which might include a simple analog amplifier as the detector followed by a separate analog-to-digital converter. In the case of a successive approximation analog-to-digital converter, an amplifier to serve as the comparator is required. In the present system, a single amplifier senses the voltage at the node 24 and senses the comparator in the analog-to-digital converter. Also, with the comparator A as an integral part of the analog-to-digital converter amplifier noise which would otherwise be amplified by an analog amplifier is eliminated. Also, the digital successive approximation register provides a convenient source of digitally stored error information such as the signal V_VAR,CAL.

The sensing capacitor C_S could have been coupled to the node 24 above without a reference capacitor C_R. However, the use of a reference capacitor is by far preferred in most applications to minimize the effects of capacitance variations from chip to chip and such other variables as temperature.

In one embodiment the reference capacitor C_R remains constant while the sensor capacitor C_S is allowed to vary with variations in pressure. In the initial construction of the capacitors, it is preferred that the capacitances of both capacitors be equal. With equal capacitances, the reference capacitor C_R and the sensor capacitor C_S, which are made under the same conditions as well as on the same chip, will tend to track or drift together with variations in temperature. Thus, the measured capacitive differences between the capacitors are independent of fluctuations resulting from variations in temperature and the like. In that embodiment, the test sequence discussed above with respect to FIGS. 1 and 2 can be used to advantage in that the voltage applied to C_S during the SAR routine is zero.

In other sensors, the capacitors C_R and C_S may both vary with a sensed parameter and e coupled differentially to the node 24. Such a sensor has, for example, been suggested for detection of shear stress. An illustration of the structure of the capacitors is illustrated in FIG. 3. In that device, the upper plates of the capacitors C_R and C_S are formed on a laterally moving plate 60, and the opposite plates are fixed to a substrate 62. As the plate 60 moves to the right, for example, the effective area of the capacitor C_S increases and the effective area of the capacitor C_R decreases. The capacitances of the two capacitors thus vary oppositely due to lateral displacement. A particularly advantageous measurement sequence for that sensor is to initially apply positive and negative reference voltages V_R and V_S (FIG. 5) to respective capacitors C_R and C_S. Then, when the switch S_C is open, the applied voltages are switched to zero for the successive approximation routine. The resultant voltage V_VAR,MEAS which nulls the voltage V.sub. X is then,

VVAR,MEAS =±VREF (CR -CS)/CC   (18)

Note that a different sequence utilizing different voltages has yielded the same results as before. This sequence has particular advantage where both capacitors are sensor capacitors because it allows both to have zero voltage applied during the SAR routine.

The switching sequence can be completely generalized. The voltages are

V_p =voltage at bottom plate of C_p

V_Rn =voltage at bottom plate of C_R in Step n

V_Sn =voltage at bottom plate of C_S in Step n

V_VAR,CAL =voltage applied to C_C to calibrate

V_VAR,MEAS =voltage applied to C_C in measurement

V₊ =voltage reference at the positive input terminal of the comparator

V_x =voltage at the sensitive node 24

V_os =offset voltage of the amplifier

In step 1, S_C is closed and the specified voltages are applied. It is assumed that V₊ and V_p never change. With the feedback loop closed, V_x is forced to V₊ +V_os. The charge on the top node becomes ##EQU1## In step 2, the switch is opened and the SAR/DAC feedback loop forces V_x back to V₊ +V_os. The expression for the charge at the top node becomes ##EQU2## If additional charge Q_other other than from the capacitors is to be taken into account (such as MOS switch charge injection or residual polarization), then by charge conservation,

Q1 +Qother =Q2 

It is easily seen that all terms involving C_p,V_os, and V₊ cancel. Solving for V_DAC,MEAS yields ##EQU3## This is the general form of the measurement. If the difference in capacitance between C_R and C_S is desired, then appropriate choices of voltages can be chosen. To eliminate the effect of Q_other, V_DAC,CAL must be chosen to equal Q_other /C_C. But a priori we do not know Q_other. But from equation 26, if V_VAR,CAL is set to zero, V_R1 =V_R2, and V_s1 =V_S2, then we can measure the value

-Qother /CC 

Setting V_VAR,CAL to the negative of this value and choosing appropriate values of V_R1, V_R2, V_S1, and V_S2, equation 26 will yield a voltage proportional to the difference of C_R and C_S In fact, V_VAR,CAL can be set to any value. If it is set equal to the negative of the value obtained by measuring the charge injection plus the capacitive mismatch, then complete cancellation can result, and the measured voltage will be zero. This is apparent from the equation. If we can independently measure the terms in equation 26, then they can each be cancelled by adjusting the value of V_VAR,CAL. All or some of the terms can be cancelled by changing V_VAR,CAL.

Equation 22 can easily be derived from the general form of equation 26. For the measured DAC voltage to be proportional to the difference in C_R and C_S, the following relation between the applied voltages must be true:

(VR1 -VR2)=-(VS1 -VS2)≠0

If the only voltages available are ±V_REF and 0, the total possible number of switching sequences is ten. The following table shows different values of V_R1,2 and V_S1,2 so that a difference in capacitance can be measured. Notice that sequences 1-8 yield the same form as equation 22. Sequences 9 and 10 have an extra constant of 2 since both ±V_REF are used throughout the steps. Dual sequences suitable for measuring voltage change due to hysteresis are sequences (1,5), (2,6), (3,7), (4,8) and (9,10).

______________________________________SWITCHING SEQUENCESSequence   VR1 Vs1   VR2                              VS2______________________________________1       0        VREF  VREF                              02       0        0          VREF                              -VREF3       0        0          -VREF                              VREF4       0        -VREF -VREF                              05       VREF            0          0      VREF6       VREF            -VREF 0      07       -VREF            VREF  0      08       -VREF            0          0      -VREF9       VREF            -VREF -VREF                              VREF10      -VREF            VREF  VREF                              -VREF______________________________________

FIGS. 4 shows an embodiment of the reference capacitor C_R and the sensor capacitor C_S on a chip for pressure sensing applications. To the right, upper plate 50 overlays four lower plates 52. The plates 50 and 52 are made of conductive material. Four air gaps 54 separate the upper and lower plates and 52. Since an air capacitor is a function of space and area, four parallel capacitors C_R /4 are formed. The sum of the capacitances equals the total capacitance of the reference capacitor C_R.

To the left of FIG. 4, an upper plate 56 overlays four lower plates 58. For this capacitor C_S, a single air gap 60 separates the upper and lower plates 56 and 58. Again, four capacitors C_S /4 are in parallel with each other, and the sum of the capacitances of the four capacitance values equal the total capacitance of the sensor capacitor C_S.

The construction difference between the sensor capacitor C_S and the reference capacitor C_R is that the upper plate 56 of each of the four capacitors C_R /4 of the reference capacitor C_R is mechanically more rigid than the upper plate 56 of the sensor capacitor C_S. Thus, the upper plate 50 of the reference capacitor will not deform as easily to pressure variations as will the upper plate 56 of the sensor capacitor C_S. The actual design of the capacitors should take into consideration the amount of pressure variations that are sought to be detected. Preferably, the deformation of the upper plate of the sensor capacitor is limited to 10 percent.

Although it is desirable to match the two capacitors as closely as possible, capacitance difference between the two stuctures will occur. Variations of mismatches from chip to chip can be calibrated by an initial test which initially measures the capacitive difference by the method described above at one or more known sensed levels. The initial capacitive difference measured is in terms of a voltage variation and that variation can be stored in a non-volatile register 42 for use in all subsequent measurement. This variation can be included in the calibration voltage V_VAR,CAL in measurement. Thus, any mismatches in manufacture can be nullified during actual use. This avoids laser trimming, which is often used to perfect matches in manufacture. Single or multiple point calibration is possible.

While the invention has been particularly shown and described with reference to the preferred emobidments thereof, it will be understood by those who are skilled in the art that there are changes in form and detail that may be made without departing from the spirit and scope of the invention as defined by the appended claims. For example, by appropriately choosing the values of the reference volta V_REF and the coupling capacitor C_C, the maximum dynamic range of the DAC can be utilized.

The DAC 40 may also be coupled back to the non-inverting input of the comparator A. Such an arrangement is less desirable, however, because the capacitor C_C serves as a natural voltage divider. Also, by always bringing V_X back to zero, any possible changes in voltage offset of the comparator due to variations in the input voltage are overcome.

The switch S_C could also be coupled to ground rather than to the output of the comparator. However, error which would then result from the voltage offset of the comparator would have to be reckoned with using the approach suggested for nullifying injected charge. Also, the voltage offset could be large and be beyond the capture range of the analog-to-digital convertor.

Although the invention has been described particularly with respect to measurements which provide the difference in capacitances between two matched capacitors, more complex sensing capacitor arrangements including multiple capacitors connected to provide both sums and differences may be designed.