Multiplier circuits专利检索-双极结型晶体管电气元件和设备专利检索查询-专利查询网

Multiplier circuits

阅读：80发布：2023-06-09

专利汇可以提供Multiplier circuits专利检索，专利查询，专利分析的服务。并且A gain control or multiplier circuit in which an input operational amplifier has a pair of feedback paths through respective collector-emitter circuits of opposite conductivity type transistors to form a first bipolar circuit for converting an input signal to a log form by virtue of the log-linear transfer characteristics of the transistors. Each transistor of the first circuit has connected to it another transistor for converting the log signal into its antilog. A second operational amplifier is used as an output buffer for the resulting combined output signals from the antilog transistors. One version employs a bias circuit connected between the emitters of the first bipolar circuit transistors to adjust quiescent current. Another version uses a neutralization circuit to pump currents into the input summing junctions of both operational amplifiers to adjust for capacitive storage effects. In all cases, a control voltage is summed with the log signal by applying the voltage to the bases of the log and antilog converting transistors, thereby controlling the gain between the two operational amplifiers.，下面是Multiplier circuits专利的具体信息内容。

权利要求

1. An electrical gain control system including a first bipolar circuit for providing first output signal which is logarithmically related to an input signal thereto; means for summing a gain control signal with said first output signal; a second bipolar circuit connected to said first circuit for providing a second output signal which is an anti-logarithmic function of the sum of said first output signal and gain control signal.

2. A system as defined in claim 1 wherein said first circuit comprises a first summing operational amplifier having a pair of negative feedback paths, and a first pair of opposite conductivity type semiconductor devices each disposed to control conduction in a respective one of said feedback paths, each of said devices having a log-linear transfer characteristic.

3. A system as defined in claim 2 wherein said semiconductor devices are transistors having substantially matched Vbe characteristics and said transistors are mounted on a common heat sink.

4. A system as defined in claim 2 wherein said second circuit comprises a second pair of opposite conductivity type semiconductor devices each connected to the output of a respective one of said first pair of semiconductor devices so as to provide an output signal which is a function of the antilogarithm of the output signals from said first pair of semiconductor devices.

5. A system as defined in claim 4 wherein said semiconductor devices of said second pair are transistor mounted on a common heat sink and have substantially matched Vbe characteristics.

6. A system as defined in claim 4 wherein all of said semiconductor devices are transistors, each pair having substantially matched Vbe characteristics, and all are mounted on a common heat sink.

7. A system as defined in claim 1 wherein said means for summing said control signal comprises a control signal terminal connected to control gain of said system for input signals of one polarity and means connected to said terminal for providing an inverted form of said control signal and connected to control gain of said system for input signals of opposite polarity.

8. A system as defined in claim 6 wherein said means for applying said control signal comprises a control signal terminal connected to the base of one transistor of at least one of said pairs, and an inverter having its input connected to said control terminal and its output connected to the base of the other transistor of said one of said pairs.

9. A system as defined in claim 6 wherein said means for applying said control signal comprises a control signal terminal connected to the bases of one transistor of said first pair and one transistor of said second pair, and an inverter having its input connected to said control terminal and its output connected to the bases of the other transistors of said first and second pair.

10. A system as defined in claim 4 including a bias control circuit connected to control quiescent currents in said transistors at a value showing sufficient ft to meet a desired frequency response of said system.

11. A system as defined in claim 10 wherein said bias control circuit comprises a biasing transistor emitter-collector connected between the emitters of the transistors of said first pair, and a biasing network connected to said biasing transistor so that the latter exhibits a temperature coefficient of Vbe which matches the sum of the Vbe temperature coefficients of said transistors of said first and second pairs of their quiescent collector current values.

12. A system as defined in claim 4 including a neutralizing circuit for compensating said system for the total effective collector-emitter capacitances of the semiconductor devices of both said first and second bipolar circuits.

13. A system as defined in claim 12 including second summing operational amplifier havings its input connected to the outputs of said second pair of devices, and wherein said neutralizing circuit comprises an inverter having its input connected to the output of said first operational amplifier and its output coupled to the summing junction inputs of both said first and second operational amplifiers.

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