Output buffer circuit
专利汇可以提供Output buffer circuit专利检索，专利查询，专利分析的服务。并且PURPOSE: To obtain a fast output signal by composing an output buffer circuit of a push-pull circuit which becomes high in impedance at non-output timing and a MISFET which supplies a current at the time of a power-side level output at output timing.
CONSTITUTION: When output timing signal (ϕ
1 ) is at level "1", NOR gates NR
1 and NR
2 of output buffer circuit 1 turn OFF push-pull output circuit MISFETs Q
1 and Q
2 while generating no outputs, so as to make input-output terminal P
1 high in impedance. When signal (ϕ
c ) is at level "0", FETs Q
1 and Q
2 are turned ON according to levels "1" and "0" of information D to be outputted, thereby outputting "1" or "0" to terminal P
1 . Then, MISFETQ
3 supplies the output current of output buffer 4 at the opposite side when signal (ϕ
c ) is "1" and operates in the same way as FETQ
1 according to information D when the signal is "0", so as to support the supply of a "1"-level output current, thereby flowing a current needed for acceleration when a "1"-level output is generated. Consequently, acceleration can be realized by the minimum FET size even when the input current is prescribed such as a TTL circuit.
COPYRIGHT: (C)1979,JPO&Japio，下面是Output buffer circuit专利的具体信息内容。
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