Multilayer insulation integrated circuit structure
阅读：256发布：2023-07-20
专利汇可以提供Multilayer insulation integrated circuit structure专利检索，专利查询，专利分析的服务。并且A planar semiconductor integrated circuit chip structure containing a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extends into the chip to provide the active and passive devices of the circuit. The surface is passivated with an insulative structure containing at least two layers with a metallization pattern for interconnecting the integrated circuit devices formed on the first layer and via holes passing through the second or upper layer into contact with various portions of this metallization pattern. The via holes are arranged so that a majority of the holes are disposed above surface regions having such impurity types and concentrations that would form Schottky barrier contacts with the metal of contacts formed in said via holes. Accordingly, if during the formation of the via holes by etching through the second layer, there is an attendant further etching through the first layer to the surface of a semiconductor region, said region will form a Schottky barrier contact with the metal deposited in the via holes, which contact will act to prevent a short circuit between the metallization and the surface region.，下面是Multilayer insulation integrated circuit structure专利的具体信息内容。
1. In a planar semiconductor integrated circuit chip structure comprising a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extend into the chip to provide the active and passive devices of the circuit, a first layer of insulative material covering said surface, a plurality of electrical contacts extending through openings in said insulative layer respectively to said regions, a metallization pattern formed on said first insulative layer connected to said contacts, a second layer of insulative material covering said first layer, said second layer having a plurality of via holes extending therethrough, and a plurality of metallic electrical contacts to said metallization pattern formed in and coextensive with said via holes, the improvement wherein the majority of the via holes in said second layer are disposed above surface regions having such impurity types and concentrations that would form Schottky barrier contacts with the type of metal of the contacts formed in the via holes, and said majority of the via holes have a horizontal dimension at least equal to the horizontal dimension of the metallization directly below said majority of the via holes.
2. The integrated circuit structure of claim 1 wherein substantially all of the via holes are disposed above surface regions having impurity types and concentrations such that would form Schottky barrier contacts with the type of metal of the contacts formed in the via holes.
3. The integrated circuit structure of claim 2 wherein the surface regions above which said via holes are disposed have a maximum impurity C.sub.0 of 10.sup.18 /cm.sup.3.
4. The integrated circuit structure of claim 3 wherein the regions above which said via holes are disposed are N type regions.
5. The integrated circuit structure of claim 4 wherein said planar surface is the surface of an N type epitaxial layer, and the N type regions above which the via holes are disposed are portions of said epitaxial layer proper.
6. In a planar semiconductor integrated circuit chip structure comprising a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extend into the chip to provide the active and passive devices of the circuit, a first layer of insulative material covering said surface, a plurality of electrical contacts extending through openings in said insulative layer respectively to said regions, a metallization pattern formed on said first insulative layer connected to said contacts, a second layer of insulative material covering said first layer, said second layer having a plurality of via holes extending therethrough, and a plurality of metallic electrical contacts to said metallization pattern formed in and coextensive with said via holes, the improvement wherein at least one of said via holes has a horizontal dimension at least equal to the horizontal dimension of the metallization of said first layer directly below said at least one of said via holes and further extends through said first layer, and the metallic contact in said via hole extends into contact with a region at said surface directly below said via hole, said region having an impurity type and concentration such that said metallic contact forms a Schottky barrier contact with said surface region.
7. The integrated circuit structure of claim 6 wherein said surface region with which the Schottky barrier contact is made has a maximum C.sub.0 of 10.sup.18 /cm.sup.3.
8. The integrated circuit structure of claim 7 wherein said surface region with which the Schottky carrier contact is made is an N type region.
9. The integrated circuit structure of claim 6 wherein substantially all of the via holes are disposed above surface regions having impurity types and concentrations such that would form Schottky barrier contacts with the type of metal of the contacts formed in the via holes.
10. The integrated circuit structure of claim 9 wherein the surface regions above which said via holes are disposed have a maximum impurity C.sub.0 of 10.sup.18 /cm.sup.3.
11. The integrated circuit structure of claim 10 wherein said planar surface is the surface of an N type epitaxial layer, and the N type regions above which the via holes are disposed are portions of said epitaxial layer proper.
12. In a planar semiconductor integrated circuit chip structure comprising a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extend into the chip to provide the active and passive devices of the circuit, a first layer of insulative material covering said surface, a plurality of electrical contacts extending through openings in said insulative layer respectively to said regions, a metallization pattern formed on said first insulative layer respectively connecting each of a plurality of voltage supplies having different levels to different regions through said contacts during the operation of the integrated circuit, a second layer of insulative material covering said first layer, said second layer having a plurality of via holes extending therethrough, and a plurality of metallic electrical contacts to said metallization pattern formed in said via holes, the improvement wherein the majority of the via holes in said second layer are disposed above surface regions having such impurity types and concentrations that would form Schottky barrier contacts with the type of metal of the contacts formed in the via holes, and the voltage levels respectively applied to metallization contacting the via hole contacts and to the said surface regions above which the via holes are disposed would be sufficient to reverse bias said Schottky barrier contacts and said majority of the via holes have a horizontal dimension at least equal to the horizontal dimension of the metallization directly below said majority of the via holes.
13. The integrated circuit structure of claim 12 wherein the surface regions above which the via holes are disposed have a maximum C.sub.0 of 10.sup.18 /cm.sup.3.
14. The integrated circuit structure of claim 13 wherein said planar surface is the surface of an N type epitaxial layer, and the N type regions above which the via holes are disposed are portions of said epitaxial layer proper.
15. The integrated circuit structure of claim 13 wherein substantially all of the via holes are disposed above surface regions having impurity types and concentrations such that would form Schottky barrier contacts with the type of metal of the contacts formed in the via holes.
16. The integrated circuit structure of claim 1 wherein said first and second layers comprise substantially the same material.
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