Low power, high speed, pulse width discriminator专利检索-肖特基结肖特基二极管二极管电子零件及设备专利检索查询-专利查询网

Low power, high speed, pulse width discriminator

阅读：739发布：2023-07-26

专利汇可以提供Low power, high speed, pulse width discriminator专利检索，专利查询，专利分析的服务。并且A pulse width discriminator which compares a received pulse with a reference pulse of specified width and produces an output pulse whenever the received pulse width is less than the width of the reference pulse. The reference pulse is generated by a monostable circuit triggered by the leading edge of the received pulse. The received pulse and the reference pulse are applied to two inputs of a logic gate circuit which produces the output pulse. To provide very low standby power requirements for battery operation, the transistor circuits constituting the discriminator are so designed that the transistor currents in the quiescent states of the circuits are practically zero. As part of the low power design, the monostable circuit comprises a complementary arrangement of two transistors both of which are nonconductive in the stable state. Delays in the discriminator are reduced to a minimum by the use of Schottky barrier diodes in shunt to the collector-base junctions of certain transistors.，下面是Low power, high speed, pulse width discriminator专利的具体信息内容。

权利要求

1. A pulse width discriminator for producing an output pulse whenever the width of a substantially rectangular input pulse is less than a specified width comprising: a differentiating circuit to which said input pulses are applied for deriving sharp trigger pulses coincident with the leading edges of said input pulses; a monostable circuit comprising first and second junction transistors having bases of opposite conductivity types, means connecting each transistor in the circuit configuration of a common emitter stage having an output circuit including the collector and emitter of the transistor and an input circuit including the base and emitter of the transistor and constructed to provide zero emitter-base bias, a direct current coupling between the output circuit of said first transistor stage and the input circuit of said second transistor stage, and a direct current blocking regenerative feedback coupling between the output circuit of said second transistor stage and the input circuit of said first transistor stage comprising a capacitor and a resistor connected in series between the collector of said second transistor and the base of said first transistor; means including a diode for applying said trigger pulses to the input circuit of said first transistor stage, said diode being poled to reject pulses of polarity opposite to that of the trigger pulses and the base conductivity type of said first transistor being that for which the trigger pulse produces a forward voltage at the emitter-base junction; an inverter comprising a third junction transistor having a base conductivity type opposite to that of the base of said second transistor, and means connecting said third transistor in the circuit configuration of a common emitter stage having an output circuit including the collector and emitter of the transistor and an input circuit including the base and emitter of the transistor and constructed to provide zero emitter-base bias; a direct current coupling between the input circuit of said third transistor stage and the output circuit of said second transistor stage, said coupling including a direct current connection between the base of said third transistor and the collector of said second transistor; a NAND gate comprising a fourth junction transistor having a base conductivity type opposite to that of the base of said third transistor, means connecting said fourth transistor in the circuit configuration of a common emitter stage having an output circuit including the collector and emitter of the transistor and an input circuit including the base and emitter of the transistor and constructed to provide zero emitter-base bias, gate input terminals A and B, a two-terminal network consisting of two series connected diodes, means directly connecting that terminal of said network to the base of said fourth transistor that provides a common direction of forward current flow for the diodes and the base-emitter junction of the transistor, a resistor connected between the input terminal A and the other terminal of said network, a diode poled oppositely to the diodes of said network connected between the input terminal B and the said other terminal, and a gate output terminal connected to the collector of said fourth transistor; a direct connection between the collector of said third transistor and input terminal A of said NAND gate; and means for applying said input pulses to the input terminal B of said NAND gate, the output terminal of the NAND gate constituting the output terminal of the pulse width discriminator.

2. Apparatus as claimed in claim 1 in which the first and last mentioned diodes are Schottky barrier diodes and, in addition, Schottky barrier diodes connected in shunt to the collector-base junctions of said first, second, and third transistors, the anode of the diode in each case being connected to the P-type transistor electrode.

3. Apparatus as claimed in claim 2 in which the input and output pulses of the pulse width discriminator are negative-going pulses, in which the said first and third transistors are PNP transistors, and in which the said second and fourth transistors are NPN transistors.

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Low power, high speed, pulse width discriminator

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