Semiconductor memory element
阅读：265发布：2023-07-29
专利汇可以提供Semiconductor memory element专利检索，专利查询，专利分析的服务。并且A semiconductor memory element for use in a memory device having high speed data read out. A semiconductor region of one conductivity type is provided on a substrate of an opposite conductivity. A first electrode is in ohmic contact with the semiconductor region and a second electrode is coupled to the semiconductor region through a rectifying barrier such as a Schottky barrier or a PN Junction.，下面是Semiconductor memory element专利的具体信息内容。
1. A memory circuit employing semiconductor memory elements comprising a plurality of write line wires, a plurality of row wires, a plurality of read line wires, a plurality of insulating gate type field effect transistors disposed at the intersections of a matrix formed by said write line wires and said row wires, each of said transistors having a substrate of one conductivity type, a thin semiconductor layer of an opposite conductivity type provided on one face of said substrate and insulated electrically therefrom, a first electrode in ohmic contact with said semiconductor layer, a second electrode electrically connected to said semiconductor layer through a rectifying barrier, an insulating gate film covering a part of the surface of said semiconductor layer between said first and second electrodes, said gate film including electron-trapping centers and trapping centers therein where an electric field exceeding a critical point is applied to said gate film, and a gate electrode provided on said gate film, a plurality of diodes disposed at said intersections of said matrix, means for connecting the gate electrode of each of said transistors to a selected one of said write line wires, means for connecting a source electrode of each of said transistors to a selected one of said row wires, means for connecting one of the electrodes of each of said diodes to a drain electrode of one of said transistors, and means for connecting the other electrode of each of said diodes to a selected one of said read line wires.
2. A semiconductor memory element comprising a substrate of one conductivity type, a thin semiconductor layer of an opposite conductivity type provided on one face of said substrate and insulated electrically therefrom, a first electrode in ohmic contact with said semiconductor layer, a second electrode provided on said semiconductor layer through a rectifying barrier, an insulating gate film covering a part of the surface of said semiconductor layer between said first and second electrodes, said gate film including electron-trapping centers and trapping electrons therein when an electric field exceeding a critical value is applied thereacross, a gate electrode provided on said gate film, means for supplying a current between said first and second electrodes through a part of said semiconductor layer under said gate film, the direction of said current passing through said semiconductor layer being limited to the forward direction of said rectifying barrier, and means coupled to said gate electrode for applying an electric field exceeding said critical value across said gate film, whereby a high impedance is produced against said current in said semiconductor layer under said gate film when said electric field is applied across said gate film.
3. The memory element of claim 2, in which said rectifying barrier is a Schottky barrier.
4. The memory element of claim 2, in which said rectifying barrier is a PN junction.
5. The memory element of claim 2, in which said semiconductor region is an epitaxial layer grown on said substrate, and said insulating gate film is an alumina film.
6. The memory circuit of claim 5, further comprising a plurality of insulating regions of said one conductivity type provided in said semiconductor layer for electrically dividing said semiconductor layer into a plurality of individual semiconductor memory elements.
7. The memory circuit of claim 6, further comprising regions of said opposite type formed in said substrate and positioned beneath said first and second electrodes.
8. The memory element of claim 5, in which said rectifying barrier is a Schottky barrier.
9. The memory element of claim 5, in which said rectifying barrier is a PN junction.
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